XC3000

This application note describes the basic flow and issues to note when performing HDL simulation with Alliance Series software. The goal of this document is to familiarize the user with some of the concepts, but it should not be considered a replacement for the Xilinx or HDL simulator documentation.

This application note describes the mature Xilinx product families and highlights their differences.

In the Spartan™ XC3000, XC4000, and XC5200 device families, Xilinx offers several evolutionary and compatible generations of Field Programmable Gate Arrays (FPGAs). This overview describes two aspects of Xilinx FPGAs: What logic resources are available to the user, and how the devices are programmed.

Clarifies why the overshoot/undershoot limit includes both magnitude and duration. Applies to mature FPGA families only.

Beware of hold time problems, because they can lead to unreliable, temperature-sensitive designs that can fail even at low clock rates.

All Xilinx SRAM-based FPGAs can be in-system configured and reconfigured an unlimited number of times. This application note describes the procedures for reconfiguring mature Xilinx FPGAs.

This application note covers several related subjects: How does a Xilinx FPGA power up, and how does it react to power supply glitches? What can be done to maintain configuration during loss of primary power? What can be done to secure a design against illegal reverse engineering?

Xilinx FPGAs can be configured in a common daisy chain structure, where the lead device generates CCLK pulses and feeds serial configuration information into the next downstream device, which in turn feeds data into the next downstream device, etc. There is no limit to the number of devices in a daisy chain, and XC3000™, XC4000™, Spartan™, and XC5200™-series devices can be mixed freely with only one constraint: the lead device must be a member of the highest order family used in the chain.

These guidelines describe the configuration process for all members of the XC3000™, XC4000™, XC5200™, and Spartan™ FPGA devices and their derivatives. The average user need not understand or remember all these details, but should refer to the debugging hints when problems occur.

This application note reviews the differences between the XC5200™ and XC2000™/XC3000™ families, recommends approaches for converting XC2000/XC3000 designs to the XC5200 architecture, and provides a methodology to migrate designs easily in multiple CAE environments.

This application note defines three metrics to describe FPGA device capacity: Maximum Logic Gates, Maximum Memory Bits, and Typical Gate Range. It also describes the methodology used to determine these values.

This application note discusses binary-to-BCD and BCD-to-binary conversions that are performed between serial binary values and parallel BCD values.

The phase comparator described in this application note permits phase-locked loops to be constructed using FPGA devices that require only an external voltage-controlled oscillator and integrating amplifier.

This application note discusses various approaches available for implementing state machines in FPGA devices, in particular, the one-hot-encoding scheme for medium-sized state machines.

This application note contains additional information for designing with the XC3000™ series of FPGA devices. This information supplements the data sheets, and is provided for guidance only.

This fully synchronous, non-loadable, binary counter uses a traditional prescaler technique to achieve high performance. Typically, the speed of a synchronous prescaler counter is limited by the delay incurred distributing the parallel Count Enable. This design minimizes that delay by replicating the LSB of the counter. In this way even the small longline delay is eliminated, resulting in the fastest possible synchronous counter.

A simple state machine is used to adapt the output of two photo-cells to control an up/down counter. The state machine provides hysteresis for counting parts correctly, regardless of change in direction.

A simple algorithm is described for determining the depth of logic, in CLBs, that can be supported at a given clock frequency. The algorithm is suitable for XC3000 Series or XC4000 Series FPGA devices.

Harmonic Frequency Synthesizer: Uses an accumulator technique to generate frequencies that are evenly spaced harmonics of some minimum frequency. Extensive pipelining is employed to permit high clock rates. FSK Modulator: A modification of the Harmonic Frequency Synthesizer that automatically switches between two frequencies in accordance with an NRZ input.

CLBs are used to emulate IEEE 1149.1 Boundary Scan. The FPGA device is configured to test the board interconnect, and then reconfigured for operation.

CLBs are used to emulate IEEE 1149.1 Boundary Scan. The FPGA device is configured to test the board interconnect, and then reconfigured for operation.

While XC3000 series FPGA devices do not provide RAM, it is possible to construct small register-based FIFOs. A basic synchronous FIFO requires one CLB for each two bits of FIFO capacity, plus one CLB for each word in the FIFO. Optional asynchronous input and output circuits are provided. Design files are available for two implementations of this design. The fastest of the two implementations uses a constraints file to achieve better placement.

The design strategies for loadable and non-loadable binary counters are significantly different. This application note discusses the differences, and describes the design of a loadable binary counter. Up, down and up/down counters are described, with lengths of 16 and 32 bits. Design files are available for all six versions.