XC9500

This application note describes how to drive LEDs using Xilinx CPLDs.

Mixed signal systems require logic parts that can operate with two power supplies. XC9500™ CPLDs are designed to operate in either mixed 5V/3.3V systems or 5V-only systems. To handle both conditions, care has been taken to ensure that designers need not introduce elaborate circuitry to guarantee that 5V and 3.3V power supplies rise or fall in any particular sequence. This application note describes the underlying XC9500 circuitry to give designers the understanding they need to best use these CPLDs.

This introduction covers the basics of VHDL as applied to CPLDs. Specifically included are those design practices that translate well to CPLDs, permitting designers to use the best features of this powerful language to extract the best performance from CPLD designs.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

Describes the bahavior of CPLDs during power up.

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature. (For Virtex™ FPGAs, see XAPP135.) For additional data, see the Xilinx™ IBIS files.

This application note discusses XC9500XL™ device use in multi-voltage systems.

This application note covers the basics of how to use Verilog as applied to Complex Programmable Logic Devices. Various combinational logic circuit examples, such as multiplexers, decoders, encoders, comparators, and adders are provided. Synchronous logic circuit examples, such as counters and state machines are also provided.

Previous generations of Xilinx FPGAs supported a Master Parallel Configuration Mode which allowed the FPGA to configure itself directly from a parallel (byte wide) PROM. The Virtex™ family of Xilinx FPGAs does not utilize a Master Parallel mode. This application note describes a simple interface design to configure a Virtex device from a parallel EPROM using the SelectMAP configuration mode.

This application note describes an enhanced procedure for utilizing the fast bulk-erase capability of the XC95216™ and XC95108™ devices on the HP 3070 tester.

Most Xilinx CPLDs, PROMs, and FPGAs have an IEEE Standard 1149.1 (JTAG) port. Xilinx devices with a JTAG port are in-system programmable (ISP) through the JTAG port. The ISP feature is beneficial for fast prototype development. This application note describes a short list of considerations needed to get the best performance from your ISP designs.

This application note describes the mature Xilinx product families and highlights their differences.

All Xilinx FPGA families can be configured through a serial interface. This application note describes a simple, low-cost design to configure any Xilinx FPGA in a serial configuration mode using a Xilinx XC9500™ CPLD and any parallel PROM.

This application note illutrates the building of embedded test instruments into XC9500™ CPLDs.

This application note helps designers understand the XC9500™ architecture and learn how to get the best performance from these devices.

This application note describes how to use the XC9500™ timing model. All XC9500 CPLDs have a uniform architecture and an identical timing model, making them very easy to use and understand. To determine specific timing details, users need only compare their paths of interest to the architectural diagrams and, using the timing model presented here, perform a simple addition of incremental time delays.

This application note discusses basic design considerations for in-system programming of multiple XC9500 devices in a boundary scan chain, and shows how to design systems that contain multiple XC9500 devices as well as other IEEE 1149.1-compatible devices.

This application note explains the XC9500™ boundary scan interface and demonstrates the software available for programming and testing XC9500 CPLDs. An appendix summarizes the JTAG programmer operations and surveys the additional operations supported by XC9500 CPLDs for in-system programming.

This application note discusses the in-system programming speed of the XC9500™ devices.

This application note describes how to program XC9500™ devices in-system, using standard Serial Vector Format (SVF) stimulus files.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

This application note describes how to enter timing constraints for CPLDs, and how to verify that your timing contraints have been met.

This White Paper shows a method for calculating how much TTL logic can be fit on a Xilinx CPLD.

This white paper gives an overview of ISDN modem technologies and how Xilinx high volume programmable devices can be used to implement complex system level glue in ISDN modem designs.

This white paper gives an overview of digital modem technologies and how Xilinx high volume programmable devices can be used to implement complex system level glue in digital modem designs.

This paper provides an overview of satellite modem technologies and standards, and discusses how the Internet is driving the deployment of this technology. The Xilinx device families targeted at these high volume applications include XC9500 CPLDs and Spartan-II FPGAs.

This paper provides an overview of Internet audio technologies and how Xilinx high-volume programmable devices can be used to overcome some of the significant challenges facing the designers of portable players. The Xilinx device families targeted at these high-volume applications include CoolRunner CPLDs and Spartan FPGAs.

This white paper focuses on the market size for the various printer technologies, both by performance and geographic region. It then discusses the basics of the technologies, to give a view of their capabilities, limitations and future directions. It will then focus on exactly where Xilinx XC9500XL CPLDs and Spartan FPGAs play a vital role in this important market, then take a look into the future direction it is headed with Internet influence and the new photographic quality printers and MFPs.