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Course Description

In this course you will learn about project structure, process windows, various ISE® software design flows, and Xilinx Synthesis Technology (XST). You will examine XST synthesis and use the XST constraints file in the Project Navigator GUI. You will learn about the Engineering Capture System (ECS) and the State Diagram Editor and ISE Simulator tools.

Level

Fundamental

Training Duration

1 day

Who Should Attend?

Digital designers who use ISE software extensively and who need to learn the major aspects of the new ISE 10.1 design tools

Prerequisites

• Basic knowledge of the VHDL or Verilog language
• Basic knowledge of Virtex™ FPGA architecture

Recommended

• Basic knowledge of Virtex® and/or Spartan®-3E FPGA architecture

Software Tools

• Xilinx ISE Foundation™ 10.1 software

Skills Gained

After completing this training, you will be able to:

• Create a new Project Navigator project in the ISE software
• List the design flows available in the ISE software
  
• Access and modify XST synthesis options
  
• Create a schematic design by using the Engineering Capture System (ECS) schematic entry tool
  
• Create a symbolic state machine by using the State Diagram Editor
  
• Create testbenches and simulate a design using the TestBench Wizard and the ISE Simulator

Course Outline

Day 1

• Course Agenda
• Projects in the Project Navigator
• Lab 1: Projects in the Project Navigator
• HDL Synthesis and XST
• Lab 2: XST Synthesis Options
• ECS: Engineering Capture System
• Lab 3: ECS
• State Diagram Editor
• ISE Simulator
• Lab 4: ISE Simulator and the State Diagram Editor
• Additional Features
• Summary

Lab Descriptions

• Lab 1: Projects in the Project Navigator – Gain comprehensive hands-on experience with the HDL flow in the ISE software. Create a new project, add source files, synthesize a design, and use the error navigation feature.
• Lab 2: Synthesis Options – Modify XST synthesis properties, read synthesis reports to compare the synthesis results, and use the snapshot utility.
• Lab 3: ECS – Perform the basic tasks of the schematic editor, such as adding symbols, connecting symbols with wires, naming wires and buses, adding I/O markers, and using the Xilinx CORE Generator™ tool with ECS.
• Lab 4: ISE Simulator and the State Diagram Editor – Perform the simulation and verification process of the design cycle. Demonstrate how these tools are incorporated into the ISE tools.