The 10 Gigabit Ethernet 802.3ae standard has a number of  features which are outlined below: 

• Preserves the 802.3 Ethernet frame format 

• Preserves the minimum and maximum frame size of the current Ethernet standard 

• Supports full duplex operation only

• Specifies an optional media independent interface (XGMII) to connect a 10 Gbps capable MAC to a 10 Gbps PHY

• Specifies an optional application unit interface (XAUI) which improves and simplifies the connection between a 10 Gbps capable MAC and a 10 Gbps PHY

• Supports a speed of 10 Gbps at the MAC interface 

• Defines two families of PHYs – LAN and WAN
  

An Ethernet Media Access Control (MAC), Layer 2 of the OSI model, connects to the PHY (Layer 1) physical media (optical or copper). Ethernet architecture further divides the PHY into a Physical Media Dependent (PMD) and a Physical Coding Sublayer (PCS).  
(An example of a PMD is an optical transceiver.)  The PCS is made up of coding (e.g., 8b/10b) and serializer or multiplexing functions.

The 802.3ae specification defines two PHY types: the LAN PHY and the WAN PHY. The WAN PHY is simply an optional extended operating feature added to a LAN PHY.   These PHYs are solely distinguished by the PCS. 

The 10 Gigabit LAN PHY is intended to support existing Gigabit Ethernet applications at ten times the bandwidth.

The WAN PHY differs from the LAN PHY by including a simplified SONET/SDH framer in the WAN Interface Sublayer (WIS).  Because the line rate of SONET OC-192/SDH STM-64 is within a few percent of 10 Gbps, it is possible to implement a MAC that can operate with a LAN PHY at 10 Gbps or with a WAN PHY payload rate of approximately 9.29 Gbps. 

Chip Interface (XAUI and XGMII) 

Among the many features defined in the 10 Gigabit Ethernet draft standard is the XAUI (pronounced "Zowie") interface.  The "AUI" portion is borrowed from the Ethernet Attachment Unit  Interface. The "X" represents the Roman numeral for ten and implies ten gigabits per second. The XAUI is a low pin count, self-clocked serial bus designed as an interface extender for the 74 signal wide interface (32-bit data paths for each of transmit and receive) XGMII. The XAUI may be used in place of, or to extend, the XGMII in chip-to-chip applications typical of most Ethernet MAC to PHY interconnects. The lower pin count, simplicity and superior signal integrity properties of XAUI make it the interface of choice, and its integration with the Xilinx 10 Gigabit Ethernet MAC helps designers to reduce the complexity and costs for 10GBASE-X systems.