The IMS and MWC events were virtual, but demos are real. Watch demo videos now!

November 16, 2021  

Editor’s Note: This content is contributed by David Brubaker, Sr. Product Line Manager of Zynq UltraScale+ RFSoC at Xilinx


The COVID-19 outbreak has severely limited industry travel since 2020, but Xilinx has continued to present new Radio IP for Zynq® UltraScale+™ MPSoC and RFSoC devices at many virtual events. I know that it can be difficult to attend an entire virtual event due to daily work commitments; to make these events more accessible, Xilinx has video recordings available online.

Let me highlight recent Xilinx video demos presented at the International Microwave Symposium (IMS) 2021 and Mobile World Congress (MWC) 2021.

First, Xilinx presented two video demos at IMS 2021.

1) The latest DPD IP (v11), correcting nonlinear effects of C-band GaN macro-level power amplifiers (PA) using long-term memory coefficients in the DPD algorithm.

2) A first look at the Zynq RFSoC DFE device, a cost and power-efficient single-chip 5G O-RU DFE device. The good news is that RFSoC DFE devices are shipping now, and they will be in full production by the end of 2021. 

Second, Xilinx showcased four videos at MWC 2021.

1) A detailed introduction to the Zynq RFSoC DFE device that integrates key 5G IP in hard IP format to reduce power consumption and cost for a 5G infrastructure solution yet retains programmable logic to adapt to 5G dynamic requirements and enable unique customization and differentiation of your design.

2) A demo of Xilinx 2nd generation telco T2 accelerator card for open vRAN solutions. The Xilinx T2 telco card is a dedicated look-aside L1 accelerator card that supports LDPC decoding up to 12GB/s and encoding up to 35GB/s using PCIe® Gen 4. 

3) Versal based 5G Beamforming Solution. 5G massive-MIMO (multiple input multiple output) beamforming requires huge processing power, and the Versal® adaptive compute acceleration platform (ACAP) is used to implement a 5G FR1 64T64R massive-MIMO solution. The beamforming leverages the AI Engines (AIE) vector processor to complete real-time matrix computations.

A full O-RAN demo with Keysight and Cisco, including control, user, synchronous, and management planes.

Lastly, I invite you to check out the recent Xilinx webinar Crash Course: From Evaluation to Design with Zynq® UltraScale+™ RFSoCs, which is available online at Xilinx webinar portal


If you need more information, please contact your local Xilinx representative.