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DesignCon 2019

Conference Participation

Principals from Xilinx engineering will be presenting in the following technical sessions to discuss research, findings and technology breakthroughs across a breadth of high performance I/O and system design methodologies.

Boot Camp – Power Integrity Hands-On Simulation & Measurement
Tuesday, January 29
9:00 AM – 4:30 PM | Ballroom E

This boot camp combines simulation and measurement. See how the gigabit SI world of IoT, automotive, cloud server products, and other applications is driving new paradigms for flat impedance and not just a maximum target Z, all while demanding lower power and multiple power rails. Learn how to use impedance vs. frequency data to create measured models, estimate decoupling capacitance, and debug noise ripple on a power rail. We’ll step through the process of optimizing the decoupling of a DDR4 example and then run the PI eco-system simulation with AC and Harmonic balance to look at small signal and large signal responses.

Mode Conversion & Its Impact on 112-Gbps PAM4 Systems
Wednesday, January 30
8:00 AM – 8:45 AM | Ballroom C

As data rates trend to 112G PAM4, mode conversion becomes non-negligible as its impact is comparable to or even larger than other impairments. A simulation approach is proposed such that the mode conversion impact on the system margin is included, in contrast to the conventional method in which only pure differential signaling is modeled as facilitated by perfectly balanced and de-skewed transmit signals. Necessary changes to IBIS-AMI standards are proposed such that inclusion of mode conversion is optionally included. Detailed examples are provided to show the impact of mode conversion on link performance margin degradation.

Enabling IBIS-AMI Simulations for Systems Containing PAM4 Retimers at 112 Gbps
Wednesday, January 30
10:00 AM – 10:45 AM | Ballroom D

End-to-end system simulations of PAM4 channels with retimers are required in 112G C2M and VSR link analyses. In this paper we present a novel AMI-repeater-based modeling approach for PAM4 retimers that enables full link simulation of retimed PAM4 channels. Equalization, CDR, data recovery and jitter transfer characteristics of PAM4 retimers can be captured accurately in this approach. Simulation results of 112G PAM4 channels demonstrate that the proposed method provides more reliable system performance predictions compared to the traditional practice which simulates each channel section independently.

Elimination of Highly Reflective Structures Through Sliding Decision Feedback Equalization
Wednesday, January 30
11:00 AM – 11:45 AM | Ballroom F

Return-loss dominated high speed channels are not uncommon within the sectors that require high-reliability products such as aerospace, defense, drilling, medical, and space. In these environments, critical mechanical requirements can push electrical performance into a very challenging corner. Conventional SerDes puts a lot of emphasis on channel ISI equalization and somewhat mitigating the impact of crosstalk, while leaving serious reflections to channel designers. This paper revisits the concept of the Sliding Tap DFE (ST-DFE), and proves its applicability in high-reliability system-level solutions. We conclude with an example of a difficult impairment that is critical to product success, and its resolution.

Modeling System Signal Integrity Dynamic to Achieve Optimal Memory Performance for DDR4 & Beyond
Wednesday, January 30
11:00 AM – 11:45 AM | Ballroom B

Modeling effective bandwidth is crucial in determining performance as system memory scales to top speed DDR4 and beyond. This paper will present a new approach to cover DDR bus turnaround dynamic. The DQ bus on the controller side and the DRAM is modeled with IO behavioral model which captures the On/Off timing. Details will be presented on how to handle the necessary feature for the modeling. This approach enables the prediction of bus channel dynamics, particularly in the case of turnaround signal integrity analysis in rank-to-rank switching between DIMMs. A validation system will be used to correlate this approach.

Modeling of Critical Crosstalk Paths for High Sampling Rate RF Direct Data Converters Integrated in a Programmable RFSoC
Wednesday, January 30
2:00 PM – 2:40 PM | Ballroom G

Traditional crosstalk depression techniques such as using stripline, setting routing space between traces, and providing vertical return paths for layer transition vias and package/ connector signal pins are well applied in transceiver applications. Though these methods provide enough isolation for 100GE CR4/KR4, they are far from meeting the isolation requirement in RF applications of -100dB noise floor. This gap must be mitigated when SI engineers design RF direct sampling systems with RFSoC integrated with both transceivers and RF ADC/DACs. This paper introduces the new crosstalk depression methodology and analysis based on 3D fields simulation with ultra-low noise floor.

Top-Down Jitter Specification Approach for HBM System Optimization
Wednesday, January 30
2:00 PM – 2:40 PM | Ballroom B

This paper presents a top-down design approach for HBM system on interposer based on jitter transfer characteristics in component blocks from different suppliers in configuration. Jitter transfer functions are formulated in blocks with different jitter aspects in components to meet overall target performance in system integration. Jitter factors in Phy IO&buffer and interposer interconnects are different with interposer response to EM as major jitter factors such as crosstalk or waveform distortion, while on-die timing uncertainties are factors of silicon circuits. HBM system design is analyzed with those jitter specifications and correlated with measured jitter data collected in hardware V&C.

Partitioning of TX & RX Feedforward Equalizer for 112-Gbps Serial Links
Wednesday, January 30
2:50 PM – 3:30 PM | Ballroom G

Effective utilization of FFEs on both the TX and RX sides plays an important role in enabling 112G systems. While TX FFE is limited by peak power constraint and RX FFE amplifies input noise, the optimal partitioning of FFE on both ends of the transceiver become a crucial design choice that will impact both system performance and power consumption. To provide a more realistic and complete framework, this paper offers a more fundamental analysis and understanding of TX/RX FFE partitioning in the presence of CTLEs and DFE.

Spec-driven CTLE Model Synthesis Through Reinforcement Learning
Wednesday, January 30
2:50 PM – 3:30 PM | Ballroom C

To enable link level simulation for given CTLE specs, it is necessary to develop models to represent the behavior of these CTLE circuits under these specs. Traditionally, a lot of manual tuning and reiteration is needed to find the desirable pole/zero locations to build a CTLE transfer function to meet the spec. In this paper, given a set of frequency domain specs of CTLE, a reinforcement learning technique is used to automatically adjust the pole/zero location of the CTLE transfer function to meet the spec, which significantly reduced the manual work of finding the desired CTLE model.

Panel – FEC for 112-Gbps High Speed Serial Links & Beyond
Wednesday, January 30
3:45 PM - 5:00 PM | Ballroom G

Forward error correction (FEC) has been widely adopted by networking and storage systems. Recently its role has become more essential for high speed serial link transmission such as 56 Gbps and 112 Gbps per lane for electrical and optical interfaces. In this panel a group of speakers from cross sections of industry will share their opinions, debate the issues, and provide solutions of FEC for high speed networking and storage serial link systems.

An Efficient Power & Signal Integrity Combo Simulation & Correlation for DDR4 & Beyond
Thursday, January 31
2:50 PM – 3:30 PM | Ballroom F

Understanding the power supply integrity together with signal integrity is ever more important as the system scales to DDR4 top speed and beyond. This paper proposes an efficient combo simulation by injecting realistic power supply noise tones according to the system usage model. The power network is based on a real design and the stimulus is based on real usage model from the memory controller unit. The paper will show the method to optimally capture the necessary feature behavior for the modeling. The analysis will be correlated to an actual lab measurement in this paper.

 

Conference information

January 29 – 31, 2019
Santa Clara Convention Center
Santa Clara, CA

Ecosystem Demonstrations

Xilinx and its ecosystem will be participating in the following demos on the show floor in our partnering booths:

Molex Booth # 631

  • Xilinx 112G PAM4 Transceivers operating over Molex Impel DC backplane connectors
  • Xilinx Virtex® UltraScale+™ 58G GTM Transceivers running 58Gb/s over QSFP56-DD cabling, facilitated by Molex NearStack high-speed connector system

TE Connectivity Booth # 817

  • Xilinx Virtex UltraScale+ 58G GTM Transceiver operating over a TE SFP-DD direct attach cable
  • Xilinx Virtex UltraScale+ GTY Transceiver operating at PCIe Gen5 rates over a preliminary TE interconnect

Samtec Booth # 737

  • Xilinx 112G PAM4 Long Reach Transceiver operating over Samtech NovaRay extreme density

Luxshare Booth # 717

  • Xilinx 112G PAM4 Long Reach Transceiver operating over Luxshare Direct Attach Copper OSFP cables.