The Virtex UltraScale+ FPGA Acceleration Development Kit is an excellent starting point for hyperscale application developers.
This development kit has been discontinued per PDN advisory XCN18025 and is no longer offered for sale. The solutions targeted for this product will not be updated moving forward with limited support available from AMD.
Ideal for data center application developers wanting to leverage the advanced capabilities of Virtex™ UltraScale+™ FPGAs. This PCIe® development board is accessible in the cloud and on-premise with the frameworks, libraries, drivers and development tools to support easy application programming with OpenCL™, C, C++ and RTL through the AMD SDAccel™ Development Environment.
Featuring the XCVU9P-L2FSGD2104E FPGA
|System Logic Cells (K)||2,586|
|GTY 32.75Gb/s Transceivers||76|
Featuring the VCU1525 Board
Power & Thermal
Communication & Networking
Node locked & Device-locked to the XCVU9P FPGA, with 1 year of updates
|Vivado Design Suite Design Edition||The AMD Vivado™ Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for FPGAs and SoCs.||Node locked and device-locked to the XCVU9P FPGA, with one year of updates.
Supports partial reconfiguration
|SDAccel Development Environment||SDAccel is a development environment for OpenCL applications targeting PCIe®-based AMD FPGA accelerator cards. This environment enables concurrent programming of the system processor and the FPGA logic without the need for RTL design experience.||Node locked and device-locked to the XCVU9P FPGA, with one year of updates.|
|Dynamic Function eXchange||Dynamic Function eXchange is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption. AMD Dynamic Function eXchange technology allows designers to change functionality of the accelerator board on the fly, eliminating the need to fully reconfigure and re-establish PCIe links while reloading.||Node locked and device-locked to the XCVU9P FPGA, with one year of updates.|
|DDR4 SDRAM Controller||DDR4 SDRAM controller is a free IP core in the Vivado IP Catalog.||No-Charge IP|
|DMA for PCI Express (PCIe) Subsystem||The AMD LogiCORE™ DMA for PCI Express (PCIe) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express 3.x integrated block. The IP provides an optional AXI4 or AXI4-Stream user interface.||No-charge IP|
|AMD SmartConnect Technology||The AMD SmartConnect Technology enables unprecedented levels of performance for the UltraScale+™ device portfolio, by solving the system interconnect bottlenecks on high density, multi-million system logic cell designs.||No-charge IP|
|SDAccel Platform Reference Design for Custom Board Support||SDAccel projects are compiled against a target platform. The SDAccel Platform Reference Design is the combination of board and hardware/software infrastructure components on which the kernels of an OpenCL application are executed. This reference design is intended to be used as a starting point to help platform developers add SDAccel support for their custom PCIe boards.||No-charge IP|
Download the Xilinx Runtime and Deployment Shell.
The Xilinx runtime (XRT) is a low level communication layer (APIs and drivers) between the host and the card.
IMPORTANT: Please enter the following command before installing the XRT:
$ sudo yum-config-manager --enable rhel-7-server-optional-rpms
$ sudo yum install -y https://dl.fedoraproject.org/pub/epel/epel-release-latest-7.noarch.rpm
$ sudo yum install epel-release
The deployment shell is the communication layer physically implemented and flashed into the card.
The VCU1525 will leverage this shell for application development, though the card itself is for development only and was not qualified for volume deployment as part of an end system.
If you are a developer, download these additional files.
The shell interface for development is required if you are building your own applications.
The AMD SDAccel IDE provides a framework for developing accelerated applications.