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Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC)

Overview

Product Description

The Xilinx® Versal™ ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC Subsystem) is a high-performance, adaptable, Ethernet-integrated hard IP, targeting numerous customer networking applications. The block can be configured for up to six ports with independent MAC and PHY functions at the IEEE Standard MAC Rates from 100GE to 400GE, and an overall maximum bandwidth of 600 Gb/s. The IP supports various FECs and IEEE 1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (IEEE 1588) hardware timestamping. In addition, the IP can be configured to provide 600 Gb/s of MAC processing for up to 40 channels of user-defined bandwidth.


Key Features and Benefits

  • Supports 1 x 400GE, 3 x 200GE, 6 x 100GE, or combinations of 100 Gb/s, 200 Gb/s, and 400 Gb/s totaling up to 600 Gb/s
  • User-side segmented AXI4-Stream interface at 390.625 MHz AXI4-Stream clock
  • 40-channel time-sliced MAC capable of 600 Gb/s operation
    • Channelized option for time-sliced applications
    • Up to 40 channels supported
    • User-defined bandwidth allocation granularity
  • 80-bit, 160-bit, or 320-bit interface to the serial transceiver
  • Pause frame processing including priority-based flow control (not yet available in the Vivado IDE)
  • Optional built-in RS-FEC functionality
  • Requires license key which is available at no charge by clicking the "Get License" button above

Support

Documentation

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