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PCI/PCI-X Offerings and Software Requirements

SOFTWARE Requirements Table

LogiCORE™ Version Software Support Supported Device Families
64-bit Initiator/Target 133 MHz for PCI-X
EF-DI-PCIX-V5-SITE
v6/v5 ISE® 12.1 Virtex®-5
Virtex-4
64-bit Initiator/Target 133 MHz for PCI-X
EF-DI-PCIX-V5-SITE
v6/v5 ISE 10.1 SP3 Virtex-II Pro
Virtex-II
Virtex-E
64-bit Initiator/Target for PCI
EF-DI-PCI64-IP-SITE
v4/v3 Vivado® 2012.3 Artix®-7
Kintex®-7
64-bit Initiator/Target for PCI
EF-DI-PCI64-IP-SITE
v4/v3 ISE 14.3 Zynq®-7000
Artix-7
Kintex-7
Virtex-5 LXT / SXT / FXT / TXT / LX
Virtex-4
Spartan®-6 LX / LXT
Spartan-3A DSP
Spartan-3A
Spartan-3 / 3E
64-bit Initiator/Target for PCI
EF-DI-PCI64-IP-SITE
v4/v3 ISE 10.1 SP3 Virtex-II / II Pro
Virtex-E / Virtex
Spartan-IIE / Spartan-II
32-bit Initiator/Target for PCI
EF-DI-PCI32-IP-SITE
v4/v3 Vivado 2012.3 Artix-7
Kintex-7
32-bit Initiator/Target for PCI
EF-DI-PCI32-IP-SITE
v4/v3 ISE 14.3
 
Zynq-7000
Artix-7
Kintex-7
Virtex-5 LXT / SXT / FXT / TXT / LX
Virtex-4
Spartan-6 LX / LXT
Spartan-3A DSP
Spartan-3A
Spartan-3 / 3E
32-bit Initiator/Target for PCI
EF-DI-PCI32-IP-SITE
v4/v3 ISE 10.1 SP3 Virtex-II / II Pro
Spartan-IIE / Spartan-II
32-bit Initiator/Target for PCI Single Project Spartan Series
EF-DI-PCI32-SP-PROJ
v4/v3 ISE 14.3 Spartan-6 LX / LXT
Spartan-3A DSP
Spartan-3A
Spartan-3 / 3E
32-bit Initiator/Target for PCI Single Project Spartan Series
EF-DI-PCI32-SP-PROJ
v4/v3 ISE 10.1 SP3 Spartan-IIE / Spartan-II
PLBv46 to PCI Full Bridge
EF-DI-PCI32-SP-PROJ
EF-DI-PCI32-IP-SITE
EF-DI-PCI-AL-SITE
EF-DI-PCIX64-VE-SITE
v1.04a ISE 13.2 Virtex-5 SXT / LXT
Virtex-5 LX
Virtex-4 FX / SX / LX
Spartan-3

Download the required software from the Xilinx.com Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.

* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.

The IP cores will be fully functional for approximately 9 hours at 66 MHz and 4 hours at 33 MHz . After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again

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