Xilinx® offers the 25 Gigabit IEEE 802.3by Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications. This core is designed to the IEEE 802.3by and 25G Ethernet Consortium Schedule 3 specification and connects seamlessly to the Xilinx soft 25G Ethernet Subsystem IP on Virtex® UltraScale™, Virtex UltraScale+™, Kintex® UltraScale+, and Zynq® UltraScale+ devices.
Key Features and Benefits
Run-time switchable between IEEE802.3by and 25G Ethernet Consortium Schedule 3 specification mode
Accessible as integrated feature in the 25G Ethernet Subsystem
Configuration and status bus
Selectable AXI4-Lite interface for status Output
Transcode Bypass mode for direct access to RS encoder/decoder
Example reference design demonstrating 25G Ethernet IP with RS-FEC