Versal AI Core Series

Versal AI Core series delivers breakthrough AI inference and wireless acceleration with integrated AI engines that deliver over 100X greater compute performance than today’s server-class CPUs.

Product Advantages

Portfolio's Highest Compute for Maximum AI and Workload Acceleration

ACAP AI Core Chip Diagram

Scalar Engines

Three scalar processor types are available in Versal™ ACAPs to support diverse application needs. The application processing unit is ideal for complex applications supported by an OS, and the real-time processing unit is ideal for applications needing low latency, determinism, and real-time control. A separate platform management controller manages system boot, security, and debug.

Adaptable Engines

Programmable logic enables the development of custom computational blocks for ever-changing algorithms. The rearchitected logic in Versal ACAPs provides 4X greater density per CLB, reducing the need for costly global routing. Loaded with a wide variety of memory elements and tightly coupled with programmable I/O, the adaptable engines allow users to create powerful accelerators for any application.

Intelligent Engines

AI Engines provide up to 5X higher compute density for vector-based algorithms. Optimized for real-time DSP and AI/ML computation, AI Engines provide deterministic performance.

Enhanced DSP engines provide support for new operations and data types, including  single and half-precision floating point and complex 18x18 operations.

 

Next-Generation I/O

The Versal AI Core series combines PCIe® Gen4 compliance, CCIX support, high performance GPIO, and multirate Ethernet MACs supporting various ethernet configurations to maximize connectivity and flexibility. Additionally, Versal AI Core series devices feature rearchitected low latency 32.75Gb/s transceivers.

Integrated DDR Memory Controllers

Each integrated DDR memory controller provides up to 34.1GB/s of bandwidth with DDR4 and LPDDR4 support, and is optimized for both linear and random traffic. In combination with the programmable Network on Chip, these integrated controllers eliminate the need for soft implementations in the programmable logic, saving development time and logic resources.

Programmable Network on Chip

The programmable network on chip (NoC) provides an optimized multi-terabit interconnect between the different compute engines and integrated IP blocks present in the Versal ACAP architecture, simplifying timing closure and saving logic resources. The NoC compiler provides a streamlined programming experience while allowing users to manage latency and QoS, ensuring that critical data paths are prioritized.


See how Xilinx FPGAs and ACAPs enable AI Inference acceleration

AI Inference

Check out the Versal AI Core series evaluation kit
 

Boards & Kits

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Applications

Versal™ AI Core series devices are optimized for compute-intensive applications, specifically digital signal processing, artificial intelligence, and machine learning

 

5G Radio & Beamforming

5G Radio & Beamforming

Beamforming results in enormous signal processing requirements that need to be processed in real time. While adaptable engines are handling status control and data formatting, AI Engines and DSP Engines are processing fixed & floating point signal processing workloads for high performance parallel processing.


Data Center Compute

As convolutional neural networks continue to evolve, the challenge to keep up with increasing computational density requirements can only be addressed by the Versal AI Core series devices, which have AI Engines optimized to efficiently deliver computational density, both cost effectively and power efficiently.

Data Center Compute

Smart Cities

Video Processing for Smart Cities

Versal AI Core series devices enable video surveillance for Smart Cities, with AI Engines driving real-time license plate or facial recognition, DSP engines for video transcoding, and adaptable engines for video scaling, compression, and customization.


Medical Image Processing

Versal AI Core series accelerates parallel beamforming and real-time image processing to create higher quality images and machine-based image analysis to enable physicians and radiologists to make faster and more accurate diagnoses.

Medical Image Processing

Radar Processing

Radar Processing

Merging powerful vector-based DSP engines with AI engines in a small form factor enables advanced radars, such as active electronically scanned arrays. AI Core series devices provide terabits per second of antenna bandwidth in a single package.


Wireless Test Equipment

Real-time DSP is used extensively in wireless communications test equipment. Versal AI Engine architecture is well-suited to handle all types of protocol implementations, including 5G from the digital front end to beamforming and baseband.

Wireless Test Equipment
Product Table

Versal AI Core Series Features Overview

Scalar Engines Features

  VC1352 VC1502 VC1702 VC1802 VC1902 VC2602 VC2802
Application Processing Unit Dual-core Arm® Cortex®-A72, 48KB/32KB L1 Cache w/ parity & ECC; 1MB L2 Cache w/ ECC
Real-time Processing Unit Dual-core Arm Cortex-R5F, 32KB/32KB L1 Cache, and 256KB TCM w/ECC
Memory 256KB On-Chip Memory w/ECC
Connectivity Ethernet (x2); USB 2.0 (x1); UART (x2); SPI (x2); I2C (x2); CAN-FD (x2)

Intelligent Engines Features

  VC1352 VC1502 VC1702 VC1802 VC1902 VC2602 VC2802
AI Engines 128 248 304 300 400 0 0
AI Engines-ML 0 0 0 0 0 152 304
DSP Engines 928 1,312 1,312 1,600 1,968 984 1,312

Adaptable Engines Features

  VC1352 VC1502 VC1702 VC1802 VC1902 VC2602 VC2802
System Logic Cells 540K 797K 981K 1,586K 1,968K 820K 1,139K
LUTs 247K 372K 449K 725K 900K 375K 521K

Platform Features

  VC1352 VC1502 VC1702 VC1802 VC1902 VC2602 VC2802
NoC Master / NoC Slave Ports 10 21 21
28 28 21 21
DDR Memory Controllers 2 3 3
4 4 3 3
CCIX & PCIe® w/ DMA (CPM) - 1 x Gen4x16,
CCIX
1 x Gen4x16,
CCIX
1 x Gen4x16,
CCIX
1 x Gen4x16,
CCIX
2 x Gen5x8,
CCIX
2 x Gen5x8,
CCIX
PCIe Express® 1 x Gen4x8 4 x Gen4x8 4 x Gen4x8 4 x Gen4x8 4 x Gen4x8 4 x Gen5x4 4 x Gen5x4
100G Multirate Ethernet MAC 1 3 4 4 4 2 2
Video Decoder Unit (VDU) - - - - - 2 4
32.75Gb/s GTY or GTYP Transceivers 8 32 44
44 44 32 32
Documentation

Documentation


Versal Design Guidance and Documentation

Xilinx provides a breadth of documentation, resources, and methodologies to accelerate your development on the Versal architecture. If you’re not sure where to begin with Versal ACAPs, the Design Flow Assistant is an interactive guide to help you create a development strategy, while the Design Process Hubs are a visual and streamlined reference to all Versal documentation by design process.


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Integrated Software and Hardware Platform for All Developers

With an inherently software programmable silicon infrastructure, the Versal™ ACAP is designed from the ground up to be software-centric. The enhanced Xilinx® Vivado® Design Suite introduces a new system design methodology and development environments such as traffic analyzer, NoC compiler, data flow modeling, and more. A high-speed, unified, cohesive debug environment accelerates debug and trace across Scalar, Adaptable, and Intelligent engines.
Download Vivado Design Suite >

The Xilinx Vitis™ unified software platform provides comprehensive core development kits, libraries that use hardware-acceleration technology. The platform provides an efficient, convenient, and unified software environment from the cloud to the edge. As a proud member of the open source community, the Vitis unified software platform is entirely free and open source.
Download Vitis Unified Software Platform >

Versal Prime Series

 


Versal ACAP Evaluation Kits

Be the first to experience the Versal ACAP architecture, built from the ground-up to be natively software programmable. Through a host of tools, software, libraries, IP, middleware, and frameworks, ACAPs enable dynamically customizable accelerated computing solutions through industry-standard design flows. The Versal AI Core series VCK190 evaluation kit has everything you need to jump-start your designs.

Learn more about the Versal AI Core series VCK190 evaluation kit >


Training Courses


Versal Design Guidance and Documentation

Xilinx provides a breadth of documentation, resources, and methodologies to accelerate your development on the Versal architecture. If you’re not sure where to begin with Versal ACAPs, the Design Flow Assistant is an interactive guide to help you create a development strategy, while the Design Process Hubs are a visual and streamlined reference to all Versal documentation by design process.

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