AR# 18002


6.1 System Generator for DSP - Release Notes and Known Issues List


General Description: 

What are the known issues for System Generator v6.1?


Support Software Issues 


1. What software do I need to install System Generator for DSP? Please see (Xilinx Answer 17966)


2. Why do I get an extra cycle of latency in my design when I use Synplify 7.2.2? Please see (Xilinx Answer 16934)


3. Global clock buffers not instantiated when using Synplify 7.3. Please see (Xilinx Answer 18648)


4. Post MAP simulation fails for M-Code block, when using Synplify 7.3. Please see (Xilinx Answer 18648)


5. Why do I get simulation mismatches when I use the retiming option for the Delay Block and Synplify 7.3.4? Please see (Xilinx Answer 18643)


6. XST bus elaboration might cause interface changes. Please see (Xilinx Answer 18650)


Xilinx Block Set Issues 


1. The CIC filter exhibits overflow for inputs that use the complete dynamic bit range of the data input. To work around this problem, do not use the full dynamic range of your input. Please see (Xilinx Answer 12480)


2. Decimation filters with a down sampling of "2" and symmetry in the impulse response fail in core generation. Please see (Xilinx Answer 15685)


3. PicoBlaze fails to compile when using the Leonardo synthesis tool. Please see (Xilinx Answer 16923)


4. PicoBlaze compiler script fails when using long module names. Please see (Xilinx Answer 16924)


5. The DDS fails to generate if Phase Dithering is selected and the Phase Angle is greater than the Phase Accumulator. Please see (Xilinx Answer 16927)


6. There are simulation mismatches for the FFTx when the VOUT is low. Please see (Xilinx Answer 18645)


7. The 2n Tap Linear MAC FIR reference block causes error. Please see (Xilinx Answer 18649)


General Issues 


1. The following error is reported during generation: "Undefined function or variable." Please see (Xilinx Answer 15190)


2. Documentation for older versions of System Generator for DSP are not available after install. Please see (Xilinx Answer 18642)


3. Generation fails when simulation stop function is defined for a model. Please see (Xilinx Answer 18623)


4. User Hardware Co-Sim files disappear when installing System Generator for DSP update. Please see (Xilinx Answer 18646).

AR# 18002
Date 05/16/2014
Status Archive
Type General Article
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