Please read the documentation, because it answers questions you might have about changes to the functionality or the look from previous versions of System Generator for DSP. The AccelDSP Synthesis Tool documentation is available in PDF format at: http://www.xilinx.com/ise/dsp_design_prod/acceldsp/index.htm
AccelDSP Enhancements New LogiCORE Support for Increased Performance - Adder/Subtractor - New GUI Support for LogiCORE Parameters
Global/Project Options - "Use LogiCORE" Global/Project Option on by Default - New "LogiCORE Defaults" Global/Project Option - Enhanced Register Inputs/Outputs Option for Higher Performance - New Project Option "Ram Threshold"
Directives - Memory Map Options "sp_sync_ram" and "sp_sync_rom" are Depreciated - New Memory Map Option "Array Access Guard"
Generate Fixed Point Report Enhancements Aid in Achieving Higher Performance - Variables List Report - Loops List Report - Operators List Report
New GUI Support for LogiCORE Parameters For VHDL flows, inferred LogiCORE parameters can now be changed from the AccelDSP GUI. As shown below, simply select the associated operator from the Project Explorer window or the Fixed Point Report, then change a parameter (like Latency) in the Properties Viewer window.
Generate Fixed Point Report Enhancements Aid in Achieving Higher Quality of Results For details on enhancements to the fixed point report, see the AccelDSP Synthesis Tool User Guide section titled AccelDSP Enhancements.
For additional details on these new or changed AccelDSP options and features, see the AccelDSP Synthesis Tool User Guide section titled AccelDSP Enhancements.
FAQ - How do I switch between MATLAB versions used with AccelDSP? See (Xilinx Answer 22966). - Is there a way to terminate or kill a process once I have launched the next step in my design flow? See (Xilinx Answer 31602). - AccelDSP appears to hang when I launch it, or it takes a long time to initialize. See (Xilinx Answer 31293)
General Issues - When running the Generate RTL step, error messages occur (because of certain coding styles): "E-ERR-0009): Failed to generate RTL model from fixed-point design for unknown reasons!" or "Out of memory." See (Xilinx Answer 31098). - When I launch AccelDSP, why do I receive "Error: Could not load the syntax highlighting File.invalid command name "AppInfo::Appinfo" while executing "Appinfo::Appinfo ProductDir"? See (Xilinx Answer 30695). - Why does the FFT example design fail the verify RTL step when using ISE Simullator as the HDL Simulator? See (Xilinx Answer 32222) - Why do I receive an error message that libSecurity.dll cannot be found when launching AccelDSP? See (Xilinx Answer 32507).