AR# 34836


Virtex-6 FPGA ML605 Evaluation Kit - Known Issues and Release Notes Master Answer Record


This answer record lists all known issues with the Virtex-6 FPGA Evaluation Kit.


To begin debugging a suspected hardware issue on the ML605, please see (Xilinx Answer 40398) ML605 Evaluation Kit - Board Debug Checklist.

To see the Design Advisories associated with the ML605, please see (Xilinx Answer 43767) Design Advisory Master Answer Record for Virtex-6 FPGA ML605 Evaluation Kit.

The ML605 Board Debug Checklist and ML605 Design Advisory Master Answer Record form part of (Xilinx Answer 43745) Xilinx Boards and Kits Solution Center - available to address all questions related to Xilinx Boards and Kits.

Board and Kits Related Issues

(Xilinx Answer 33569) - ML605 Boards - Where can I find the USB UART driver?
(Xilinx Answer 35675) - ML605 - Decoupling for jitter attenuator on PCIe clock
(Xilinx Answer 34385) - ML605 - IIC pull-ups needed when using FMC card
(Xilinx Answer 37579) - What device do I have on my board? Is it an Engineering Sample or Production Silicon?
(Xilinx Answer 38786) - ML605 - Differential termination might be needed on fanout buffer
(Xilinx Answer 39210) - Boards - Directory structure of CF card changed
(Xilinx Answer 40350) - Development Boards - Do Series 6 Evaluation Kits support eFUSE?
(Xilinx Answer 40705) - Development Boards - BRD GUI on Windows 7
(Xilinx Answer 50596) - Xilinx Evaluation Kits - PCIe cards - CE requirements for PC test environment
(Xilinx Answer 52773) - Virtex-6 FPGA ML605 Evaluation Kit - MIG Reference Design - Valid Data Window Test Fails for Byte Groups 3 and 7
(Xilinx Answer 55805) - Xilinx Evaluation Kits - Board becomes non-operational when TI USB Interface EVM is attached
(Xilinx Answer 56811) - Xilinx Evaluation Kits - How do I reprogram the TI power controllers on my board to the factory defaults?
(Xilinx Answer 61849) - 6 series and 7 series Xilinx Evaluation Kits - Known Issues and Release Notes Master Answer Record for the Texas Instruments Power Solution
(Xilinx Answer 65024)- Xilinx Evaluation Kits - Compact Flash Solution

Documentation Related Issues

(Xilinx Answer 34405) - ML605 Hardware User Guide (UG534) - GTXE1 Package placement is incorrectly shown on page 33
(Xilinx Answer 35330) - ML605 - NDS336P symbol is incorrect in schematics
(Xilinx Answer 35332) - UG534 - Figure 1-17 shows incorrect symbol for NDS(Xilinx Answer 35332)336P
(Xilinx Answer 40883) - ML605 - UG534 Onboard Power Regulators
(Xilinx Answer 42251) - UG534 - Pinout for Main IIC Bus connecting to NV Memory
(Xilinx Answer 44109) - UG534 - GTX QUAD_115 reference clock connections are swapped in Figure 1-10

PCI Express Related Issues

Note: All boards with Engineering Sample silicon must use the v1.3 rev 2 integrated block wrapper and ISE 12.1 or later versions of the tools. 

To obtain the v1.3 rev 2 patch, see (Xilinx Answer 36552) Virtex-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - Non-default User Interface Frequency not supported when the ML605 Development Board option is selected.

(Xilinx Answer 34033) - Virtex-6 FPGA Integrated Block Wrapper for PCI Express - The v1.4 core might fail to train reliably in Engineering Sample silicon
(Xilinx Answer 34009) - Virtex-6 FPGA ML605 Board - PCI Express Link Will Not Train; Implementations for PCI Express Must Use the v1.3 Integrated Block Wrapper for PCI Express
(Xilinx Answer 33127) - Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - UCF constraint for sys_clk incorrect for ML605
(Xilinx Answer 40279) - ML605 - PCIe reset pull-up spec

Design Tools Related Issues

(Xilinx Answer 34181) - Hardware co-sim for the ML605 board fails due to MAP erroring out with a new error message regarding the MMCM we instantiate.
(Xilinx Answer 33604) - 11.3 ChipScope Pro IBERT - "ERROR: sim - Error: Par failed. Timing for this design was not met. Reduce the number of GTs enabled."
(Xilinx Answer 34683) - 11.x ChipScope, Virtex-6 FPGA - IBERT parameter sweep tests show errors in the middle of the eye
(Xilinx Answer 33849) - Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKFBOUT_MULT_F values
(Xilinx Answer 35426) - Virtex-6 FPGA Integrated Block for PCI Express - The v1.3, v1.3 rev 1, v1.4, and v1.4 rev 2 wrapper might not link train on startup when using ISE Design Suite 11.5 or later
(Xilinx Answer 52472) - 14.x - 6 Series Boards and Kits - Are TRDs and Example Designs available for 14.x?

11.5 Design Tools Information

11.5 includes important updates and supports production devices for the Virtex-6 and Spartan-6 device families.
However, several work-arounds might be required for Virtex-6 and some Spartan-6 FPGA customers using ISE 11.5 design tools.
Please review (Xilinx Answer 32147) before you upgrade to ISE 11.5 design tools. These work-arounds are addressed in ISE 12.1 design tools, released in May 2010.

12.1 Design Tools Information

At this time, ML605 Evaluation Kits are not shipped with 12.1 version of ISE Design Suite.
The reference designs (shipped with the kits and available on-line) are only supported in version 11.4 of the tools.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43750 Xilinx Boards and Kits Solution Center - Top Issues N/A N/A

Child Answer Records

Associated Answer Records

AR# 34836
Date 09/18/2017
Status Active
Type Release Notes
Boards & Kits
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