AR# 43846


Spartan-6 FPGA SP605 Evaluation Kit - Interface Test Designs


I am attempting to exercise the interfaces on the Spartan-6 FPGA SP605 Evaluation Kit.

What tests can be run to ensure that the interfaces are working correctly?


Spartan-6 FPGA SP605 Evaluation Kit Documentation and Reference Designs referenced below can be found on the SP605 Support page.

Feature Test Design Notes
Configuration Interfaces
Configuration Mode Pins SP605 User Guide (UG526) Page 57, Configuration Options - Assumes SPI, BPI, and System ACE properly configured.
See XTP061 for restoring contents to default.
Configuration USB JTAG port SP605 BIST (XTP062) Page 52 - "Program SP605 with BIST Design".
Configuration BPI Flash SP605 BIST (XTP062) Page 21 - Option 4
Configuration SPI Flash SP605 BIST (XTP062) Page 21 - Option 9
Configuration System ACE SP605 BIST (XTP062) Page 18 - Assumes a properly constructed System ACE card. See XTP061 for restoring contents.
Board Feature Interfaces
Board DDR3 Memory SP605 BIST (XTP062) Page 21, Option 8 - Can also be tested with XTP060 (SP605 MIG Design).
Board I2C Interface SP605 BIST (XTP062) Page 21, Option 5
Board RJ45 - Ethernet SP605 BIST (XTP062) Page 21, Option 6
Board USB Serial UART SP605 BIST (XTP062) Page 13-16
Board GPIO Header Standalone Apps Test (XTP064) GPIO Header Loopback Test section
Board FMC-LPC connector XM105 User Guide (UG537) Page 29. This is the User Guide for the XM105 mezzanine debug card.
This card has DS5, DS6, and DS7 which indicate good power to the board.
Debug strategies will vary depending on the specific mezzanine card being used.
Board Power Monitoring Interface (TI PMBus) (Xilinx Answer 37561) Written for ML605, but also applicable for SP605.  Requires the TI USB EVM Adapter; see (Xilinx Answer 54022)
Board DVI PHY SP605 BIST (XTP062) Page 21 - Option C
Board PCIe Edge Connector SP605 PCIe Gen1 Design (XTP065)
Board SFP Connector SP605 IBERT Design (XTP066) Page 14 - Requires Molex 74720-0501
Transceiver Interfaces
Transceiver GTP RefCLK (differential) SP605 IBERT Design (XTP066) Choose RefCLK SMA connectors for clock (P = FPGA Pin C11, N = FPGA Pin D1, GTPA1_DUAL_X0Y0)
Transceiver GTP Transceiver SMA Connectors (differential) SP605 IBERT Design (XTP066) Pages 12 and 13
User Specified Interfaces
User LEDs SP605 BIST (XTP062) Page 21 - Option 2
User DIP switches SP605 BIST (XTP062) Page 21 - Option 7
User Pushbuttons SP605 BIST (XTP062) Page 21 - Option A
User CLK Socket Connector SP605 BIST (XTP062) Any test design in this suite uses the socket CLK, also can be used in IBERT example design (XTP066).
User SMA Connectors (differential) none available These are completely user-driven I/O. A good test would be loop back or monitoring differential I/O on a scope.
User SMA CLK Connectors (differential) none available These are completely user-drive differential clocks.
It might be possible to modify an example design to use these instead of the socketed oscillator.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43748 Xilinx Boards and Kits - Debug Assistant N/A N/A
AR# 43846
Date 01/21/2014
Status Active
Type General Article
Boards & Kits
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