AR# 50572


Zynq-7000 Example Design - Interrupt handling of PL generated interrupt


This example design implements a timer in PL, and the interrupt of the timer will ring the CPU by GIC IRQ.
Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.

A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.

It is up to the user to "update" these tips for future Xilinx tools releases and to "modify" the Example Design to fulfill their needs. 
Limited support is provided by Xilinx on these Example Designs.


Implementation Details
Design TypePS and PL
SW TypeStandalone
CPUsSingle CPU
PS FeaturesGIC, UART1
Xilinx Tools VersionVivado 2014.4 or 2016.1
Other details USB cable II or Digilent cable, mini cable, PS configuration is ZC702 template.
Address Map

Base AddressSizeBus Interface
AXI TIMER0x4280000064KS_AXI


Step by Step Instructions:

  1. Open Vivado 2014.4 or 2016.1
  2. Enter the following command in the Vivado Tcl console:
    cd {<full directory of zynq_design_bd.tcl >}
  3. Enter the following command in the Vivado Tcl console:
    source zynq_design_bd_2014_4.tcl" or "source zynq_design_bd_2016_1.tcl"
  4. After block design creation has completed, generate the output products for the block design.
  5. After the product is generated, generate the wrapper.
  6. Generate the bitstream. 
  7. After the bitstream is generated, open the implemented design.
  8. In the File menu, click Export Hardware for SDK, and check all selections.
  9. After SDK has launched, create the BSP and an empty application.
  10. Import C code to the empty application project.
  11. Set up the terminal to watch UART output.
  12. Run the application.


Note: Be careful of the interrupt ID number. 

In this design ID 61 was defined in xparameters.h.

ID mapping is different in Vivado 2013.x and Vivado 2014.x or later, See (Xilinx Answer 62107) for more details.

Expected Results:

Interrupt information will print in the terminal repeatedly.


Associated Attachments

Name File Size File Type
Pl_timer_intr_test.c 4 KB C
zynq_design_bd_2014_4.tcl 8 KB TCL
zynq_design_bd_2016_1.tcl 69 KB TCL

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51779 Zynq-7000 SoC - Example Designs and Tech Tips N/A N/A
AR# 50572
Date 05/18/2018
Status Active
Type General Article
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