AR# 51597

|

Endpoint Block Plus Wrapper for PCI Express - Master Answer Record

Description

This master answer record for the Virtex-5 Endpoint Block Plus Wrapper for PCI Express core lists all release notes, Design Advisories, Known Issues and general information answer records for different versions of the core.

_________________________________________________
This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) - Xilinx Solution Center for PCI Express

Solution

Release Notes:

(Xilinx Answer 23985) Release Notes v1.1
(Xilinx Answer 24603) Release Notes v1.2
(Xilinx Answer 25162) Release Notes v1.3
(Xilinx Answer 25493) Release Notes v1.4
(Xilinx Answer 29468) Release Notes v1.5
(Xilinx Answer 30120) Release Notes v1.6
(Xilinx Answer 30632) Release Notes v1.7
(Xilinx Answer 30980) Release Notes v1.8
(Xilinx Answer 31572) Release Notes v1.9
(Xilinx Answer 32274) Release Notes v1.10
(Xilinx Answer 32741) Release Notes v1.11
(Xilinx Answer 33278) Release Notes v1.12
(Xilinx Answer 33762) Release Notes v1.13
(Xilinx Answer 35321) Release Notes v1.14
(Xilinx Answer 42760) Release Notes v1.15

Design Advisories:

(Xilinx Answer 33580) Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express Master Answer Record
(Xilinx Answer 34444) Design Advisory for the Endpoint Block Plus Wrapper v1.13 for PCI Express - Transmit Stall Due to Link Partner Advertisement of Data Limited Completion Credits
(Xilinx Answer 33699) Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Polarity Reversal on Lane 7 Could Cause the Core Not to Train all 8 Lanes
(Xilinx Answer 33534) Design Advisory for the Endpoint Block Plus for PCI Express Wrapper v1.12 for PCI Express - Using Synplify with the Block Plus Wrapper Source Code Delivery
(Xilinx Answer 33411) Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - After warm reset, TX direction stalls forever because of deassertion of trn_tdst_rdy_n
(Xilinx Answer 33709) Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Improve Timing Closure
(Xilinx Answer 33710) Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Extended deassertions of trn_rnp_ok_n could result in completions being blocked inside the core


Known Issues/General Information:

(Xilinx Answer 30124) Endpoint Block Plus Wrapper for PCI Express - Patch updates for Endpoint Block Plus Wrapper for PCI Express
(Xilinx Answer 31164) Endpoint Block Plus Wrapper v1.8 for PCI Express - MPS of 128 or 256 bytes causes received TLP bit errors due to Expansion ROM work-around
(Xilinx Answer 31460) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - The default TXPREEMPHASIS value is incorrect for FXT devices on page 7 of the CORE Generator Customization GUI
(Xilinx Answer 32091) Endpoint Block Plus Wrapper v1.11 for PCI Express - Downstream Port model drops completions with length 64 bytes and greater
(Xilinx Answer 32727) Endpoint Block Plus Wrapper v1.11 for PCI Express - MAP fails to complete due to predictable IP placement constraints
(Xilinx Answer 32946) Endpoint Block Plus Wrapper v1.11 for PCI Express - Syntax error in x1 board_dual.v causes simulation failures
(Xilinx Answer 33850) Endpoint Block Plus Wrapper v1.13 for PCI Express - Reading and Writing Configuration Space Registers Fails
(Xilinx Answer 34706) Endpoint Block Plus Wrapper v1.15 for PCI Express - Disconnecting Packets on TX Interface when Interfacing with a link Partner Advertising Non-Infinite Completion Credits Can Eventually Stall the Transmit Interface
(Xilinx Answer 37246) Endpoint Block Plus Wrapper v1.14 for PCI Express - Possible inbound packet loss if a 8b10b error occurs while previous packet is being written into receive block RAM
(Xilinx Answer 31210) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Interrupt Status bit not set when generating Legacy Interrupt
(Xilinx Answer 31211) Endpoint Block Plus Wrapper v1.12 for PCI Express - Link transitioning to L0s causes BAR settings to be reset
(Xilinx Answer 31646) Endpoint Block Plus Wrapper v1.14 for PCI Express - Dual core UCF problems
(Xilinx Answer 31647) Endpoint Block Plus Wrapper v1.12 for PCI Express - Dual core implement_dual.bat file missing
(Xilinx Answer 31843) Endpoint Block Plus Wrapper v1.9 for PCI Express - Power management transition from D0 to D3hot to D0 can cause transmit stall
(Xilinx Answer 31850) Endpoint Block Plus Wrapper v1.12 for PCI Express - Simulation testbench writes to incorrect address for Device Control Register
(Xilinx Answer 33400) Endpoint Block Plus Wrapper v1.12 for PCI Express - ModelSim simulation results in numerous signals trimmed from the wave dump
(Xilinx Answer 33401) Endpoint Block Plus Wrapper v1.12 for PCI Express - "ERROR:sim:159 - An internal error has occurred - when disabling TX_DIFF_BOOST
(Xilinx Answer 33410) Endpoint Block Plus Wrapper v1.12 for PCI Express - Compatibility issues with ISE Project Navigator because of PIO_EP.v file module declarations and 64-bit interface ifdef declaration
(Xilinx Answer 33421) Endpoint Block Plus Wrapper v1.11 for PCI Express - Core generated for x2 lanes, Virtex-5 FXT or TXT, will not link up
(Xilinx Answer 33937) Endpoint Block Plus Wrapper for PCI Express - The implement.sh[bat] file errors out during synthesis of the wrapper files
(Xilinx Answer 33939) Endpoint Block Plus Wrapper v1.12 and later for PCI Express - How to create an NGC file of the Block Plus Wrapper files
(Xilinx Answer 51600) Endpoint Block Plus Wrapper v1.15 for PCI Express - Example Design Simulation Fails for x8 Configuration Article
(Xilinx Answer 42368) Virtex-5 Integrated PCI Express Block Plus - Debugging Guide for Link Training Issues
(Xilinx Answer 46888) Virtex-5 Endpoint Block Plus for PCI Express - Debugging and Packet Analysis Guide with Downstream Port Model and PIO Example Design
(Xilinx Answer 47109) Virtex-5 Endpoint Block Plus for PCI Express - Value for cfg_interrupt_mmenable signal Article
(Xilinx Answer 30107) Endpoint Block Plus Wrapper for PCI Express - What output should be expected when running the PIO example simulation?
(Xilinx Answer 31376) Endpoint Block Plus Wrapper v1.8 for PCI Express - Transmit Lockup on First Completion Transmitted after Link Up
(Xilinx Answer 31419) LogiCORE Endpoint Block Plus for PCI Express - ML555 not recognized by system. What is the pinout for the ML555 board?
(Xilinx Answer 31704) Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Importing a v1.8 XCO to v1.9 causes "Error:sim228 -An Invalid core configuration has been detected during Customization.
(Xilinx Answer 34183) Endpoint Block Plus Wrapper v1.13 for PCI Express - How to generate an NGC from the source files
(Xilinx Answer 29236) Endpoint Block Plus Wrapper for PCI Express - How should the user application respond to requests targeting Expansion ROM? System hangs during Boot process
(Xilinx Answer 31284) Endpoint Block Plus Wrapper v1.9 for PCI Express - Per Vector Masking Bit incorrectly set inside MSI Control Register
(Xilinx Answer 32270) Endpoint Block Plus Wrapper v1.9 for PCI Express - Using non-synchronous links with Virtex-5 FXT (GTX RocketIO) could result in data errors
(Xilinx Answer 33643) Endpoint Block Plus Wrapper v1.12 for PCI Express - Cannot implement the core in Project Navigator
(Xilinx Answer 36783) Endpoint Block Plus Wrapper v1.14 for PCI Express - Finite completion attribute not set correctly

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54065 14.4 SysGen - "xlSyncLevels threw in xlMungeMaskParams: Maximum recursion limit of 500 reached..." N/A N/A
54063 14.4 System Generator for DSP - Recursion Limit Error N/A N/A
54069 LogiCORE IP Color Filter Array Interpolation (CFA) v3.0 and v4.0 - Why does the CFA fail to generate if the maximum number of columns or rows is set to larger than 1024 when using the EDK pcore in XPS? N/A N/A
N/A N/A
54577 Install - Is WebPack version 6.2 the same as Foundation ISE version 6.2 and how to get the registration ID for 6.2 ISE ? N/A N/A
N/A N/A
54678 Release Notes and Known Issues for LogiCORE IP AXI Bus Functional Models (AXI BFM) for Vivado 2012.4 and Forward N/A N/A
54677 Vivado IP Flows - Generated IP target files delivered in Vivado are always READ ONLY in the Vivado Text Editor N/A N/A
54673 MIG 7 Series DDR3 - Incorrect connection of write leveling debug signals in the ChipScope Write ILA when the debug signals are enabled N/A N/A
54205 14.x XPower Analyzer - "EXCEPTION:Pds:Pds_PdlBlock.c:319:1.24 - Mode mismatch error." N/A N/A
54206 PlanAhead - MYXILINX enviroment variable is not loaded by the PlanAhead tool N/A N/A
54209 Virtex-7 FPGA VC707 Evaluation Kit - UG885 (v1.2) - EMCCLK settings for Linear BPI Flash Memory configuration incorrect N/A N/A
5420 Alliance/Foundation 1.5i: Icons in start menu do not bring up the software. Can't find execuatble. N/A N/A
N/A N/A
54445 LogiCORE IP I/O Module - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54446 Zynq Processing System 7 IP - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54444 LogiCORE IP AXI Timebase Watchdog Timer (WDT) - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54449 LogiCORE IP Controller Area Network (CAN) - Release Notes and Known Issues for Vivado 2016.3 and older tool versions N/A N/A
54442 LogiCORE IP AXI Performance Monitor - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54447 LogiCORE IP AXI Streaming FIFO - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
N/A N/A
54544 LogiCORE Video to SDI TX Bridge Core - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions N/A N/A
54545 LogiCORE SDI RX to Video Bridge - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions N/A N/A
54543 LogiCORE IP SPDIF/AES3 - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
54540 LogiCORE IP Video Scaler - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
54548 Video over IP FEC Receiver (VoIP FEC RX) - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions N/A N/A
54549 LogiCORE IP Video over IP FEC Transmitter (VoIP FEC TX) - Release Notes and Known Issues for the Vivado 2015.1 tool and later versions N/A N/A
5454 4.2i Foundation Library Manager - When I attach a library to another project, unexpanded block errors occur in implementation tools N/A N/A
54174 Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 (ISE 14.4/Vivado 2012.4) - GTX transceiver CPLL can become inoperative on certain conditions N/A N/A
54177 2012.4 Vivado Implementation: Automatic insertion of BUFG on high fanout reset signals N/A N/A
54173 ISE Design Suite - The supported Zynq devices are incorrectly listed on the ISE Design Suite product page N/A N/A
5417 LogiCORE Direct Digital Synthesis (DDS) - What controls the effective Signal-to-Noise Ratio (SNR) of the DDS Core? N/A N/A
54274 Zynq-7000 Example Design - IP Integrator AXI3 Master N/A N/A
54279 Kintex-7 FPGA KC705 Evaluation Kit - Interface Test Designs N/A N/A
54276 CONSTRAINTS : How can I constrain asynchronous paths from the clock resources? N/A N/A
N/A N/A
54038 Vivado - ERROR: [Common 17-161] Invalid option value 'BITSTREAM.CONFIG.UNUSEDPIN' specified for 'name' N/A N/A
54036 Zynq-7000 SoC ZC706 - UG963 (v1.0) - SW11 switch settings incorrect for SD card boot N/A N/A
54037 Zynq-7000 SoC ZC706 - UG961 (v1.0) - SW11 switch settings incorrect for SD card boot N/A N/A
5403 Constraints - Is there a way to add internal pull-ups/pull-downs in a device using the UCF (User Constraints File) or Constraints Editor? N/A N/A
54651 32/64-bit Initiator/Target for PCI (7 series) - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
N/A N/A
54712 VITA 57.1 FMC standard - FMC_VIO_B_M2C signal is supplied by the FMC card N/A N/A
54710 MIG 7 Series - DDR3 - Controller hangs on a read-modify-write operation N/A N/A
N/A N/A
54810 Vivado - Unable to use (read-only) XCI IP core files (under version control) in Vivado non-project mode N/A N/A
54811 v1.03a - axi_intc - Fast interrupt does not work with AXI_INTC N/A N/A
54817 ILA 2.0 - Debug IP from 2012.x does not appear in 2013.1 N/A N/A
54813 IP Release Notes and Known Issues for LogiCORE IP AXI4-Stream Interconnect Cores for Vivado 2013.1 tools and newer tool versions N/A N/A
54958 Design Assistant for Vivado Synthesis - Help with synth_design switches and their description N/A N/A
54956 14.5 iMPACT - iMPACT is unable to play the SVF file with an exception "Data Mismatch" N/A N/A
54953 Test AR 2 for CMS Testing (updated 3/20/2013) N/A N/A
54951 Vivado - How can I report BUFHCE usage in the device? N/A N/A
54952 Test AR (take 2) N/A N/A
N/A N/A
54682 IP Release Notes and Known Issues for LogiCORE AXI DMA Core for Vivado 2013.1 and newer tool versions N/A N/A
54687 14.4 EDK - SDK not able to build a BSP for Zynq devices when used from the PlanAhead tool N/A N/A
54683 2012.4 Vivado Implementation Tools - How do I do manual routing in Vivado GUI? N/A N/A
N/A N/A
54782 Vivado - In the Vivado text editor, is there a way to toggle the case of a group of characters? N/A N/A
54785 LogiCORE IP Tri-Mode Ethernet MAC v5.5 and earlier - IFG Adjust values that are smaller than 9 will result in TX IFG of 12 when core is generated with half duplex support N/A N/A
N/A N/A
54143 Kintex-7 FPGA Embedded Kit - Compiling webserver application cannot find “lmfsimage” N/A N/A
54140 7 Series Transceivers - What are the termination values of transceiver ports before the device is configured? N/A N/A
54146 Logicore IP Aurora 8B10B/64B66B - Recommendation for new designs N/A N/A
N/A N/A
54317 Vivado - Non-project IP core "does not match the current project part" N/A N/A
N/A N/A
54418 LogiCORE IP AXI BRAM Interface Controller - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54419 LogiCORE IP AXI External Peripheral Controller (EPC) - Release Notes and Known Issues for Vivado 2013.4 and older tools versions N/A N/A
54414 LogiCORE IP MicroBlaze Micro Controller System (MCS) - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54415 LogiCORE IP Mailbox - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
54412 IP Release Notes and Known Issues for LogiCORE AXI TFT Controller for Vivado 2013.4 and older tool versions N/A N/A
54413 LogiCORE IP MicroBlaze Debug Module (MDM) - Release Notes and Known Issues for Vivado 2013.4 and older tool versions N/A N/A
5441 LogiCORE PCI - What addressing mode is supported during memory burst transactions? N/A N/A
54556 14.4 SDK - Program FPGA button is unresponsive in Zynq projects N/A N/A
54553 2012.4/14.4 - XPS - Enabling GPIO on EMIO Interface Not Possible When Using Processing System 7 v4.02a N/A N/A
54551 Vivado Synthesis - How does Vivado Synthesis treat imported core netlists? N/A N/A
54559 14.4 - EDK - XPS - How can I make the AXI Datamover's M_AXIS_MM2S and S_AXIS_S2MM bus interfaces external? N/A N/A
N/A N/A
54282 7 series GTX - What is the power consumption of the eye scan circuit? N/A N/A
54285 Soft Error Mitigation (SEM) v3.5 - Requirements for Support of Larger Densities of SPI Flash N/A N/A
54283 2013.2 Vivado - Vivado interprets EDIF netlist keywords as case sensitive N/A N/A
54284 2012.x - Signals created with a generate statement not saved to WFCG file N/A N/A
N/A N/A
54380 14.4 - XPS - XADC Instantiation option is grayed out in the config IP GUI for AXI 7 Series DDRx IP N/A N/A
54381 Xilinx Programming Cables - Platform Cable USB and Parallel Cable IV - Driver install FAQ N/A N/A
54384 MIG 7 Series DDR3 - changing DATA_PATTERN in sim_tb_top.v does not work as expected N/A N/A
54382 Digilent Programming Cables - Driver Install FAQ N/A N/A
54383 Artix-7 FPGA AC701 Evaluation Kit - Interface Test Designs N/A N/A
N/A N/A
54044 Vivado 2012.4/ISE 14.4 - Device Pack (2012.4.1) Release Notes N/A N/A
54042 14.5 Install - I am unable to download the ISE 14.5 Design Suites install image N/A N/A
N/A N/A
54668 LogiCORE IP QSGMII - Release Notes and Known Issues for Vivado 2013.1 and Forward N/A N/A
54663 LogiCORE IP FIFO Generator - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
54661 Vivado 2013.1 and Forward - IP Release Notes and Known Issues for Distributed Memory Generator N/A N/A
54669 10-Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
54662 LogiCORE IP Block Memory Generator - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
54660 2012.4, 2013.1, 2013.2 Vivado - "ERROR: [Common 17-69] Command failed: This design contains one or more evaluation cores for which bitstream generation is not supported..." N/A N/A
AR# 51597
Date 01/28/2016
Status Active
Type General Article
IP
People Also Viewed