To identify the silicon on your ZC706, please see (Xilinx Answer 37579).
To begin debugging a suspected hardware issue on the ZC706, see (Xilinx Answer 54013) Zynq-7000 SoC ZC706 Evaluation Kit - Board Debug Checklist.
To view the Design Advisories associated with the ZC706, see (Xilinx Answer 53979) Design Advisory Master Answer Record for Zynq-7000 SoC ZC706 Evaluation Kit.
The ZC706 Board Debug Checklist and ZC706 Design Advisory Master Answer Record form part of (Xilinx Answer 43745) Xilinx Boards and Kits Solution Center - available to address all questions related to Xilinx Boards and Kits.
Known Issues
Board and Kit Related Issues
| (Xilinx Answer 53305) | Zynq-7000 SoC ZC706 Evaluation Kit - SD card is empty |
| (Xilinx Answer 53862) | Zynq-7000 SoC ZC706 Evaluation Kit - SW4 settings for the ZC706 |
| (Xilinx Answer 54022) | How can I order a TI USB Interface Adapter EVM from Texas Instruments? |
| (Xilinx Answer 55805) | Xilinx Evaluation Kits - Board becomes non-operational when TI USB Interface EVM is attached |
| (Xilinx Answer 56811) | Xilinx Evaluation Kits - How do I reprogram the TI power controllers on my board to the factory defaults? |
| (Xilinx Answer 58053) | Zynq-7000 SoC ZC706 Evaluation Kit - JTAG chain not recognized unless SW2 pushed |
| (Xilinx Answer 58420) | ZC706 - Does the ZC706 Evaluation Platform Support SDIO Cards? |
| (Xilinx Answer 58987) | Zynq-7000 SoC ZC706 Evaluation Kit - FMC HPC CC pins not connected to Clock Capable pins |
| (Xilinx Answer 59748) | Zynq-7000 SoC ZC706 Evaluation Kit - PCB Revision Differences |
| (Xilinx Answer 61849) | 6 Series and 7 Series Xilinx Evaluation Kits - Known Issues and Release Notes Master Answer Record for the Texas Instruments Power Solution |
| (Xilinx Answer 64906) | Zynq-7000 SoC ZC706 Evaluation Kit - Issues when restoring the ZC706 flash |
| (Xilinx Answer 64890) | Xilinx Evaluation Kits - AC701 and ZC706 rev 2.0 - Restoring power controllers |
| (Xilinx Answer 65207) | Zynq-7000 SoC ZC706 Evaluation Kit - Changes from rev 1.2 to rev 2.0 |
| (Xilinx Answer 67507) | Xilinx Boards and Kits - Power Supply Information |
| (Xilinx Answer 68695) | Zynq-7000 SoC ZC706 Evaluation Kit - Rev 2.0 schematics VCCF3V3 connection |
Documentation Related Issues
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 52344) | Zynq-7000 SoC ZC706 Evaluation Kit - UG954 - Which SD Interface Level Shifter is present on the ZC706 Evaluation Platform? | v1.0 | v1.1 |
| (Xilinx Answer 53453) | Zynq-7000 SoC ZC706 Evaluation Kit - GPIO_LED_0 not listed in Table 1-27 of UG954 (v1.1) | v1.1 | v1.2 |
| (Xilinx Answer 53863) | Zynq-7000 SoC ZC706 Evaluation Kit - UG961 (v1.0) - SW4 settings to run the BIST on the ZC706 | v1.0 | v4.0 |
| (Xilinx Answer 54036) | Zynq-7000 SoC ZC706 - UG963 (v1.0) - SW11 switch settings incorrect for SD card boot | v1.0 | v2.0 |
| (Xilinx Answer 54037) | Zynq-7000 SoC ZC706 - UG961 (v1.0) - SW11 switch settings incorrect for SD card boot | v1.0 | v2.0 |
| (Xilinx Answer 54105) | Zynq-7000 SoC ZC706 - ZC706 inconsistent pin assignments on FMC connector, Table 1-33 of UG954 (v1.1) | v1.1 | v1.2 |
| (Xilinx Answer 55184) | Zynq-7000 SoC ZC706 Evaluation Kit - What is the I2C bus address for the PMBUS_DATA/CLOCK signal? | v1.1 | v1.2 |
| (Xilinx Answer 58912) | Boards and Kits - Board files blocked on xilinx.com | ||
| (Xilinx Answer 66171) | Zynq-7000 SoC ZC706 Evaluation Kit - Rev 2.0 - POR calculation in schematic is not accurate | rev 2.0 | |
| (Xilinx Answer 66252) | Zynq-7000 SoC ZC706 Evaluation Kit - UG954 (v1.5) - Figure 1-32 C6 value and POR calculation is not accurate | v1.5 | |
| (Xilinx Answer 69233) | Zynq-7000 SoC ZC706 Evaluation Kit - UG954 v1.6 - Table 1-28 is inaccurate | v1.6 |
Silicon Related Issues
| (Xilinx Answer 47915) | Design Advisory Master Answer Record for Zynq-7000 SoC Devices |
PCI Express Related Issues
| (Xilinx Answer 52656) | Zynq SoC ZC706 Evaluation Kit - PCIe Targeted Reference Design - PCIe does not link up on Z77 (Ivy Bridge) platform |
| (Xilinx Answer 53740) | Design Advisory for 7 Series Xilinx PCI Express Cores - No Clock Output on TXOUTCLK at Cold Temperature |
Design Tools Related Issues
| (Xilinx Answer 52071) | Zynq-7000 SoC Impact - QSPI programming on the ZC706 (7045) requires the board to be in JTAG mode |
| (Xilinx Answer 55931) | Xilinx Evaluation Kits - What type of license is shipped with Xilinx Evaluation Kits? |
| (Xilinx Answer 60358) | 2014.1 lwIP designs for ZC702 and ZC706 both designs fail to return pings. |
USEFUL INFORMATION:
Third Party Debug Tool Information
| (Xilinx Answer 46881) | Zynq-7000 - How to setup your Third Party Debug Environment on the ZC702 Board |
| (Xilinx Answer 47767) | Zynq-7000, ZC702 - Lauterbach Startup Script |
Reference Design Information
| (Xilinx Answer 46880) | Zynq-7000 Example Design - Linear QSPI Performance (Max Effective Throughput) |
| (Xilinx Answer 46915) | Zynq-7000 Example Design - Setup the TRACE port via EMIO on the ZC702 board |
| (Xilinx Answer 50572) | Zynq-7000 Example Design - Interrupt handling of PL generated interrupt |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 43750 | Xilinx Boards and Kits Solution Center - Top Issues | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 54013 | Zynq-7000 SoC ZC706 Evaluation Kit - Board Debug Checklist | N/A | N/A |
| 37579 | Which device do I have on my Xilinx Evaluation Kit; is it an Engineering Sample (ES) or Production silicon? | N/A | N/A |
| 61849 | 6 Series and 7 Series Xilinx Evaluation Kits - Known Issues and Release Notes Master Answer Record for the Texas Instruments Power Solution | N/A | N/A |
| AR# 51899 | |
|---|---|
| Date | 05/21/2018 |
| Status | Active |
| Type | Known Issues |
| Devices |
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| Boards & Kits |
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