Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 40469)
When generating the 7 Series Integrated Block for PCI Express v1.7 core by selecting VHDL, XST results in the following error:
ERROR:Xst:2927 - Source file ../source/PCIe_portion_pipe_clock_tandem.vhd does not exist
ERROR:Xst:2927 - Source file ../source/PCIe_portion_tandem_cpler.vhd does not exist
Tandem configuration support is available only for Verilog for now. Please select 'Verilog' when generating the core.
Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
11/26/2012 - Initial release