AR# 53544

Description

Solution

To Generate SAIF for Power Analysis from ModelSim, in the generated .do file ensure the following:

• Ensure that the transport option is specified see (Xilinx Answer 9872)
   
  vsim -voptargs="+acc" -t 1ps +transport_int_delays +pulse_r/10 +pulse_int_r/10 +maxdelays -L simprims_ver -L secureip -lib work testbench glbl
   
  
• ModelSim trims some signals out of the design. To avoid this, add -voptargs="+acc":
   
  vsim -voptargs="+acc" -t 1ps +transport_int_delays +pulse_r/10 +pulse_int_r/10 +maxdelays -L simprims_ver -L secureip -lib work testbench glbl

For RTL simulation, ensure that the right options are provided to capture all of the input and output signals:

• power add -in -inout -out /testbench/UUT/*

For timing simulation, ensure that the right options are provided to capture all the signal information including the inputs, outputs, and internal signals:

• power add -in -inout -internal -out /testbench/UUT/*

After the run command, ensure that the SAIF information is captured to a file:

• power report -all -bsaif test.saif