AR# 53806

Description

How can I use the legacy design including FIR Compiler v5.0 in Vivado Sysgen?

What is the migration path for this IP and similar?

Solution

Users need to migrate their MDL first in ISE System Generator and then after completing this migration, it will be possible to open the design in Vivado System Generator.

Follow these steps:

1. Open the MDL in the latest ISE SysGen
2. Right-click on the old version of the block and select Xilinx Tools -> Upgrade Block
3. This will give you options of what version to upgrade to, if multiple upgrade options exist. Choose the latest (e.g., FIR Compiler 5.0), choose FIR Compiler 6.3
4. Upgraded block should have the same settings as the old block. You may need to reconnect the block in some cases in the MDL as connections can sometimes be broken.
5. You can now open this MDL in Vivado System Generator
6. Once open, you might need to upgrade the block or MDL for Vivado as well. Note that blocks will contain a red exclamation mark if an upgrade is required.
7. There are three options available to do this:
• From the Sysgen token, run "Model Upgrade". This produces an HTML file with a list of blocks which can be upgraded. From this HTML file, you can individually upgrade blocks or upgrade the complete MDL.
• You can-right click on the white space in the MDL file when open, select Xilinx Tools -> Upgrade Model
• Finally, you can right click on each block individually in the MDL and select Xilinx Tools -> Upgrade Block.