2. Support
  3. AR# 5550: M1.5i Virtex Timing - Timing tools are not heeding DUTY_CYCLE_CORRECTION parameter.
  4. AR# 55508: 7 Series Integrated Block for PCI Express v1.9 - Provided NCSIM simulation script with the example design does not work

AR# 55508

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7 Series Integrated Block for PCI Express v1.9 - Provided NCSIM simulation script with the example design does not work

Description

Version Found: v1.9
Version Resolved and other Known Issues: (Xilinx Answer 40469)
                                            
When running example design simulation in NCSIM with the provided script, the simulation does not work.

Solution

This is a known issue and is scheduled to be fixed in a future release of the core.

To work around this issue, follow these steps:

1. Copy cds.lib and hdl.var into /pcie_7x_v1_9/simulation/functional/
   cp -rf <>/clibs/ius/12.2/lin64/lib/cds.lib ./ 
   cp -rf <>/clibs/ius/12.2/lin64/lib/hdl.var ./
2. Add the below two lines in cds.lib file.
   UNDEFINE work
   DEFINE work ./work
3.    ./simulate_ncsim.sh

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
04/10/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40469 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 N/A N/A
AR# 55508
Date 08/26/2013
Status Active
Type Known Issues
IP
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