Version Found: MIG 7 Series v1.9
Version Resolved: See (Xilinx Answer 54025)
The MIG 7 Series DDR3/DDR2 design performs Read Leveling Calibration followed by PRBS Read Leveling Calibration to fine tune the centering of the read capture clock. In the MIG 7 Series v1.9 rtl ONLY, a specific line of code is incorrectly commented out causing the results of the PRBS Read Leveling Calibration stage (increments and decrements to the Phaser_IN blocks) to not be applied as if the stage of calibration did not run. Calibration will not fail, but the fine tuned adjustments found during PRBS Read Leveling will not be applied. This can cause read data errors post calibration. Manual modification is required within the MIG 7 Series v1.9 rtl.
This issue is resolved in MIG 7 Series v2.0. Therefore, only MIG 7 Series v1.9 requires this update.
To work around this issue, perform the following:
Standard MIG 7 Series Coregen IP:
Note for Vivado Users: If using the "Open IP Example Design" feature to generate a Vivado project with the MIG Example Design, the MIG rtl is not copied from the local project directory but rather from the Vivado tool tree. If the update was made to the local project mig_7series_v1_9_ddr_phy_prbs_rdlvl.v file, it will not be reflected in the example design Vivado project. The update must be manually made in the example design Vivado project.
EDK MIG 7 Series IP:
The Standard MIG 7 Series Coregen IP flow can be used to update the rtl in the local MIG design. However, if the example design is open, the change is not reflected. The update noted in the Standard MIG 7 Series Coregen IP section can be made to either:
When using the AXI MIG 7 Series IP, axi_7series_ddrx_v1_08_a, the location of the required update is:
Vivado Tree: C:\Xilinx\Vivado\2013.1\ids_lite\EDK\hw\XilinxProcessorIPLib\pcores\axi_7series_ddrx_v1_08_a\hdl\verilog\mig_7series_v1_9_ddr_phy_prbs_rdlvl.v
05/03/13 - Included EDK MIG 7 Series IP section
04/15/13 - Initial release