AR# 55853


Vivado Constraints - Can I embed timing constraints within my Verilog or VHDL file?


I am trying to use timing constraints inside my VHDL or Verilog files.

However, I am not seeing any messages from Vivado tools about this constraint being accepted or rejected.  I also do not see any indication from report_timing or report_timing_summary that indicates that my constraints were used.

Are in-line constraint okay for Vivado Synthesis?


Vivado tools do not support timing constraints embedded in RTL. Users should create a set_max_delay command and enter these constraints in an XDC file.

See UG903, Vivado Design Suite User Guide: Using Constraints, on the Xilinx website ( for constraint syntax and usage.

AR# 55853
Date 08/06/2013
Status Active
Type General Article
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