General Description: This warning may occur when instantiating lower levels of hierarchy using FPGA Express
Solution
This warning may be issued if multiple instantiations of a component are made and just one of those instantiations is used incorrectly. For example, if five component declarations are made and only one of those has a pin mismatch, FPGA Express will return five warnings instead of one warning message.
Check the pin declarations on all instantiations of the instance in question.