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10-Gigabit Ethernet PCS/PMA (10GBASE-R/10GBASE-KR) v4.0 and earlier - Configuration Vector - 125us timer not initialized correctly in example design
When using the Verilog or VHDL 10GBASE-R or the VHDL 10GBASE-KR example design, the configuration_vector[399:384] is tied to 0.
However, the product guide states that these bits should be 0x4c4b to set the correct 125 microsecond timer for the BER monitor state machine.
To correct this, change configuration_vector[99:384] to 0x4c4b in the example design.
This has been addressed in the 2013.4 release of the core.
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- 10 Gigabit Ethernet PCS-PMA with FEC/Auto-Negotiation for backplanes (10GBASE-KR)
- Ten Gigabit Ethernet PCS/PMA