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Zynq-7000 SoC ZC706 Evaluation Kit - Changes from rev 1.1 to rev 1.2
What changes were made to the ZC706 Evaluation Kit between revisions 1.1 and 1.2 of the PCB?
The ZC706 Rev 1.2 changes are listed below:
- Added two 0.47 uF caps to VCCPLL net, name VCCPLL net
- Updated packaged delays on all DDR3 and MIO nets
Length match tweaks due to updates to UG933:
- ULPI_Group: +/- 100 ps centered on clock: USB_CLKOUT, USB_DATA0, USB_DATA1, USB_DATA2, USB_DATA3, USB_DATA4, USB_DATA5, USB_DATA6, USB_DATA7, USB_DIR, USB_NXT, USB_STP
- RGMII_TX_Group: +/- 100 ps centered on clock: PHY_TXD0, PHY_TXD1, PHY_TXD2, PHY_TXD3, PHY_TX_CLK, PHY_TX_CTRL
- RGMII_RX_Group: +/- 100 ps centered on clock: PHY_RXD0, PHY_RXD1, PHY_RXD2, PHY_RXD3, PHY_RX_CLK, PHY_RX_CTRL
- SDIO_LS_Group: +/- 100 ps centered on clock: SDIO_CD_DAT3_LS, SDIO_CLK_LS, SDIO_CMD_LS, SDIO_DAT0_LS, SDIO_DAT1_LS, SDIO_DAT2_LS
- SDIO_Conn_Group: +/- 100 ps centered on clock: SDIO_CD_DAT3, SDIO_CLK, SDIO_CMD, SDIO_DAT0, SDIO_DAT1, SDIO_DAT2
- QSPI_Group: +/- 100 ps centered on clock: QSPI_CLK, QSPI_CS_B, QSPI_IO0, QSPI_IO1, QSPI_IO2, QSPI_IO3
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- Zynq-7000 SoC ZC706 Evaluation Kit