This is a known problem with the FIFO when the FWFT option is enabled. The hardware will work correctly, as will the HDL simulation.
You can work around this issue by generating a synchronous FIFO with FWFT enabled in the CORE Generator tool, then bringing it into System Generator for DSP as a blackbox.
Information on how to bring a core into System Generator for DSP as a blackbox can be found in the System Generator for DSP User Guide (UG639), under the Blackbox example:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/sysgen_gs.pdf
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 58034 | ISE Design Suite 14, DSP Tools (System Generator for DSP) (14.7) - Release Notes and Known Issues | N/A | N/A |
| 45811 | ISE Design Suite 13 DSP Tools (System Generator for DSP) (13.4) - Release Notes and Known Issues | N/A | N/A |
| AR# 58996 | |
|---|---|
| Date | 01/08/2014 |
| Status | Active |
| Type | General Article |
| Tools | |
| IP | |