AR# 59167


Design Advisory for MIG 7 Series DDR3 - Data rate specification changes for DIMM interfaces and data rate advisory for component interfaces


This Design Advisory is being released as a notification of pattern sensitivity that has been seen within the MIG 7 Series DDR3 designs.

When using aggressive data patterns (such as PRBS23), loss in the channel and skew within the silicon deteriorate the available margin.

Extensive testing has proven that enough margin deterioration occurs to limit reliable operation at maximum specified data rates.

This design advisory details the data rate limits and when additional design guidelines are recommended.


MIG 7 Series DDR3 DIMM Interfaces

Single Rank DIMM

Max data rate for single rank is 1600Mbps. Interfaces operating at or below 1600Mbps are not affected.

Dual Rank DIMM

Max data rate for dual rank is 1333Mbps. Interfaces operating at or below 1333Mbps are not affected.

MIG 7 Series DDR3 Component Interfaces

Designs using 1866Mbps components should contact Xilinx Technical Support to discuss additional recommended design guidelines.

Related Information

If Vivado generates the following warning message, the information outlined in this Design Advisory applies:

Warning: See DAAR 59167- additional recommendations may apply at this data rate. Please contact Xilinx Technical Support

Revision History:


  • Removed the max DDR3 Component data rate restriction of 1800 Mbps. Added additional guidelines note for 1866Mbps components
  • Max data rate for single rank DIMM set to 1600 Mbps
  • Updated with 2015.3 Vivado messaging

10/01/2014 - Updated with 2014.3 Error Messaging

08/20/2014 - Updated Related Information

06/02/2014 - Initial Release

Linked Answer Records

Master Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
61853 MIG 7 Series - Maximum frequency values in MIG tool updated in Vivado 2014.3 N/A N/A

Associated Answer Records

AR# 59167
Date 10/09/2015
Status Active
Type Design Advisory
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