The XilinxCoreLib library is used for behavioral simulation of ISE IP generated from the CORE Generator tool.
If your design includes IP generated from the Vivado IP catalog (IP.xci), you do not need the XilinxCoreLib library for simulation.
Simulation models of Xilinx Vivado IP cores are delivered as an output product when the IP is generated.
Also, when you use compile_simlib to compile the Xilinx Libraries for third party simulators, the simulation models for the Vivado IP cores are not included in the pre-compiled libraries.
In Vivado releases prior to 2014.1, if your design contains legacy ISE CORE Generator IP used in Vivado, XilinxCoreLib libraries are included to support simulating them.
These files can be found in the following locations:
(where XILINX_VIVADO is the Vivado installation path).
In Vivado 2014.1 and later, the XilinxCoreLib library sources are removed from the Vivado installation.
If you need to simulate any legacy ISE IP in a Vivado design, It is recommended to use the structural simulation file for that IP.