AR# 61201: Vivado Partial Reconfiguration - How do I debug Partial Reconfiguration designs?
AR# 61201
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Vivado Partial Reconfiguration - How do I debug Partial Reconfiguration designs?
Description
How do I debug Partial Reconfiguration (PR) designs?
Solution
Build up the PR design requirements one at a time,
checking the results at each step.
Replace the HD.RECONFIGURABLE property with the KEEP_HIERARCHY property, comment out the Pblock constraint(s), forcing the tools to maintain the module boundaries. This will allow you to avoid all of the exclusive
placement, routing containment, site blocking, and clock layout rules of
Partial Reconfiguration. Run implementation with this set and examine the results (resource
utilization, timing reports, etc.).
Add the Pblock constraints, forcing the tools to maintain the pblock boundaries Run implementation with this set and examine the results (resource
utilization, timing reports, etc.).
Change the
KEEP_HIEARCHY property to HD.PARTITION property, forcing the tools to maintain the pblock boundaries and associated insulation.
Run implementation with this set and examine the results (resource
utilization, timing reports, etc.).
If the results look good, add EXCLUDE_PLACEMENT to the pblock, forcing all static logic
outside the pblock. Run implementation with this set and examine the results (resource
utilization, timing reports, etc.). This will give a better sense of overall
density and the density inside the RP. (These properties are explained in more detail in UG909 and UG905.)
If the results look good, add CONTAIN_ROUTING to the pblock, forcing all of the RM routing to stay inside the
pblock. Run implementation with this set and examine the results (resource
utilization, timing reports, etc.). (These properties are explained in more detail in UG909 and UG905.)
Note: Please monitor your results at each step to ensure that you are on target to reach your goals. Design optimizations should
be considered to help lower the overall density and complexity at each step.