AR# 61637


Zynq-7000 SoC, SMC Parallel (SRAM/NOR) Interface Does Not Correctly Assert CS0 For 64 MB Memories


Chip Select 0 (CS0) does not go active when accessing anaddress in the range 0xE4000000 - 0xE5FFFFFF in the SRAM/NOR interface when thememory controller is configured to access a 64 MB memory device.


Impact:                      Minor. 

Work-around:        You can implement either of the following workarounds:


Work-around 1:

Description: Aboard circuitry can be implemented as a work-around for ADDR 25 inversion andChip Select assertion.

Below are the steps:

  1. Implement a two input AND gate - the two inputs come from  the MIO0 andMIO1 outputs from the Zynq-7000 SoC.
    Connect the AND gate output to the NORflash devices chip enable input.

  2. Connect the MIO0 output from the Zynq-7000 SoC to the ADDR 25 input ofthe NOR device.

  3. Configure MIO0 as Chip Select 0 and MIO1 as Chip Select 1.


Work-around 2:

Description:  A GPIO based control can be implemented for ChipSelect assertion.

Configure MIO0 as GPIO and drive constant 0.

This can be done as part of the NOR flash initialization. 

Connect it to the chipenable input of the NOR flash device.

Configurations Affected:

All Zynq devices withSRAM/NOR interface enabled for 64MB memory access. 

There is currently no plan to fix this issue.

Please refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record.


Use the PS7 Configuration Wizard fromVivado Design Suite 2014.3 OR If writing your own FSBL use work-around 2  ORupdate the board layout with workaround 1

AR# 61637
Date 05/28/2018
Status Active
Type Design Advisory
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