AR# 61638


Zynq-7000 SoC, SMC Parallel (SRAM/NOR) Interface Address Bit 25 Is Inverted For 64 MB Memories


The address bit 25 (A25) appears as 1 when accessing0xE2000000 - 0xE3FFFFFF and '0' when accessing 0xE4000000 - 0xE5FFFFFF in theSRAM/NOR interface when the memory controller is configured to access a 64 MBmemory device.



Impact:                      Minor. 


A board circuitry can be implemented as a workaround for ADDR 25 inversion and Chip Select assertion.


Below are the steps:

  1. Implement a two input AND gate - the two inputs come from  the MIO0 and MIO1 outputs from the Zynq-7000 SoC.
    Connect the AND gate output to the NOR flash devices chip enable input.

  2. Connect the MIO0 output from the Zynq-7000 SoC to the ADDR 25 input of the NOR device.

  3. Configure MIO0 as Chip Select 0 and MIO1 as Chip Select 1.


Configurations Affected:        


All Zynq devices with SRAM/NOR interface enabled for 64MB memory access. 

There is currently no plan to fix this issue.

Please refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record.


Resolution:                Implement the board level workaround


AR# 61638
Date 05/28/2018
Status Active
Type Design Advisory
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