Determining if Write Margin is Causing Data Errors
data errors are seen in pre-MIG v2.3 designs,
care should be taken to ensure the errors are due to small write margin based on the center taps selected during calibration.
- Strict adherence to all MIG PCB guidelines and careful attention to IBIS simulation must be completed first.
- The data errors should be analyzed to determine whether a write error has occurred.
Review the DDR3 Debugging Data Errors section of UG586 for assistance in isolating the data error.
- Analyze the pre-MIG 2.3 OCLKDELAY Calibration results:
- Add dbg_phy_oclkdelay_cal[254:0], "oclkdelay_calib_done", and "oclkdelay_calib_start" from "rtl/phy/mig_7series_v2_1_ddr_phy_oclkdelay_cal.v" into an ILA.
- Capture ILA waveforms for a passing reset (no write data errors) and a failing reset (write data errors) where the trigger is set to oclkdelay_calib_done.
- Determine how many edges are found, where the edges are found, where the final (center) tap is placed, and how many taps the final (center) tap moves between a working and failing case.
Signals of interest are:
- dbg_phy_oclkdelay_cal[6*dqs_i+:6] = ocal_tap_cnt_r[dqs_i][5:0]
- dbg_phy_oclkdelay_cal = ocal_rise_edge1_found_timing
- dbg_phy_oclkdelay_cal = ocal_rise_edge2_found_timing
- dbg_phy_oclkdelay_cal[65:60] = ocal_rise_edge1_taps
- dbg_phy_oclkdelay_cal[71:66] = ocal_rise_edge2_taps
- dbg_phy_oclkdelay_cal[84:79] = stg3_tap_cnt
- dbg_phy_oclkdelay_cal[219+:6] = stg2_tap_cnt
- dbg_phy_oclkdelay_cal = ocal_fall_edge1_found
- dbg_phy_oclkdelay_cal = ocal_fall_edge2_found
- dbg_phy_oclkdelay_cal[232:227] = ocal_fall_edge1_taps
- dbg_phy_oclkdelay_cal[238:233] = ocal_fall_edge2_taps
- dbg_phy_oclkdelay_cal[244:239] = ocal_rise_right_edge
* Errors are typically seen when only one edge is detected during OCLKDELAY calibration and the center tap is chosen based off of 1 known tap position.