AR# 62368


Design Advisory for MIG 7 Series DDR3 - Calibration updates in MIG 7 Series v2.3 available with Vivado 2014.4 provide additional write margin


The MIG 7 Series v2.3 DDR3 calibration algorithm available with Vivado 2014.4 includes changes that positively impact the available write margin. 

The updates are included in all MIG 7 Series v2.3 DDR3 designs.

This answer record includes information regarding the update and whether the updates are recommended within new and existing DDR3 systems.


Details on Write Side Calibration Changes:

Write DQS centering within the write DQ eye has previously consisted of finding window edges through adjustment of Phaser_OUT taps. 

The algorithm has been found across process variation to place the Phaser_OUT taps in a non-ideal (non-center) location causing the Write DQS to be shifted either left or right of the true center. 

The new algorithm uses a MMCM to perform precise phase adjustments to determine the window and place the write DQS in the true center of the write DQ eye. 
An additional MMCM is NOT added.  Instead, the MMCM already included in MIG generated designs to create the fabric clock "PHY_Clk" is also used to perform this write side calibration. 
However, a new MMCM output is added to perform the phase adjustments which requires an additional BUFG.

These updates to the write calibration logic increase the time for calibration to complete in hardware. 

Typical hardware calibration times are as follows:


Calibration Time at 400 MHz (4:1)

Calibration Time at 800 MHz (4:1)







less than 1 sec

less than 1 sec

less than 1 sec

less than 1 sec


less than 1 sec

~1 sec

less than 1 sec

~1 sec


less than 4 sec

~7 sec

less than 2 sec

less than 4 sec

*2014.2 includes updates to the read calibration algorithm.

See (Xilinx Answer 59167) for full details.

Calibration times are faster at higher frequencies because the required number of  reads and writes to perform the phase adjustment can complete faster then at a lower frequency.

Calibration time in simulation when using the FAST mode is minimally affected.

Recommendations for updating MIG Versions:

RTL changes are included for DDR3 interfaces across all frequencies. 

For new designs and those not yet in production, please update to MIG 7 Series v2.3.

For systems already in production that have completed system testing with no write margin failures, updating is recommended but not required. 

Should an update in the production cycle be available, inclusion of MIG 7 Series 2.3 is recommended.

Determining if Write Margin is Causing Data Errors:

If data errors are seen in pre-MIG v2.3 designs, care should be taken to ensure the errors are due to small write margin based on the center taps selected during calibration.

  1. Strict adherence to all MIG PCB guidelines and careful attention to IBIS simulation must be completed first.
  2. The data errors should be analyzed to determine whether a write error has occurred.
    Review the DDR3 Debugging Data Errors section of UG586 for assistance in isolating the data error.
  3. Analyze the pre-MIG 2.3 OCLKDELAY Calibration results:
    1. Add dbg_phy_oclkdelay_cal[254:0], "oclkdelay_calib_done", and "oclkdelay_calib_start" from "rtl/phy/mig_7series_v2_1_ddr_phy_oclkdelay_cal.v" into an ILA.  
    2. Capture ILA waveforms for a passing reset (no write data errors) and a failing reset (write data errors) where the trigger is set to oclkdelay_calib_done.
    3. Determine how many edges are found, where the edges are found, where the final (center) tap is placed, and how many taps the final (center) tap moves between a working and failing case. 
      Signals of interest are:
      1. dbg_phy_oclkdelay_cal[6*dqs_i+:6] = ocal_tap_cnt_r[dqs_i][5:0]
      2. dbg_phy_oclkdelay_cal[58]             = ocal_rise_edge1_found_timing
      3. dbg_phy_oclkdelay_cal[59]             = ocal_rise_edge2_found_timing
      4. dbg_phy_oclkdelay_cal[65:60]         = ocal_rise_edge1_taps
      5. dbg_phy_oclkdelay_cal[71:66]         = ocal_rise_edge2_taps
      6. dbg_phy_oclkdelay_cal[84:79]         = stg3_tap_cnt
      7. dbg_phy_oclkdelay_cal[219+:6]       = stg2_tap_cnt
      8. dbg_phy_oclkdelay_cal[225]            = ocal_fall_edge1_found
      9. dbg_phy_oclkdelay_cal[226]            = ocal_fall_edge2_found
      10. dbg_phy_oclkdelay_cal[232:227]      = ocal_fall_edge1_taps
      11. dbg_phy_oclkdelay_cal[238:233]      = ocal_fall_edge2_taps
      12. dbg_phy_oclkdelay_cal[244:239]      = ocal_rise_right_edge

      * Errors are typically seen when only one edge is detected during OCLKDELAY calibration and the center tap is chosen based off of 1 known tap position.

Additional Information:
(Xilinx Answer 59167) Design Advisory for MIG 7 Series DDR3 - Data rate specification changes for DIMM interfaces and data rate advisory for component interfaces.
(Xilinx Answer 60687) MIG 7 Series DDR3 - Calibration updates available in MIG 7 Series v2.1 released with Vivado 2014.2 that provide additional read margin for data rates above 1333Mbps
(Xilinx Answer 62615) MIG 7 Series DDR3 (IPI Flow ONLY) - Warning message generated upon IPI Upgrade - Clocking structure for MIG has been updated

Revision History:
11/19/2014 - Initial Release

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Associated Answer Records

AR# 62368
Date 01/09/2015
Status Active
Type Design Advisory
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