| TRD | NWL Expresso IP |
|---|---|
| TRD01 | v1.24 x1 Gen 1 - Bridge only (64 bit) 4 ingress & 4 egress |
| TRD02 | v1.25 x8 Gen 3 - Bridge + DMA (256 bit) 2 ingress & 2 egress & 4 CH |
| TRD03 | v1.24 x8 Gen 2 - Bridge + DMA (128 bit) 2 ingress & 2 egress & 4 CH |
ZC706 - Xilinx Zynq-7000 SoC ZC706 Evaluation Kit
PCIe Lanes / Version: x4 Gen 2, x8 Gen 1
NWL Core: AXI DMA Back-End Core (2C2S, 2S2C)
The Xilinx Zynq-7000 SoC ZC706 Evaluation Kit is shipped with a 12 hour hardware time out evaluation netlist for the Northwest Logic PCIe DMA IP.
This 12 hour hardware time out evaluation netlist allows the customer to use this Netlist IP for evaluation purposes, however after 12 hours the PCIe DMA IP will time out in the hardware.
This time-out can be reset for another 12 hours by resetting the PCIe bus.
Once evaluation of the PCIe DMA provided is complete, Northwest Logic can be contacted to obtain a Full Production license.
This Northwest Logic Hardware Time Out Evaluation PCIe DMA Core is provided and configured with an AXI DMA Back End for use in the reference design that is provided with this kit.
If a different DMA interface or configuration is required (other than what is provided with the ZC706), please contact Northwest Logic: http://nwlogic.com/info-request/
VC709 - Xilinx Virtex-7 FPGA VC709 Connectivity Kit
PCIe Lanes / Version: x8 Gen 3
NWL Core: AXI DMA Back-End Core (4C2S, 4S2C)
The Xilinx Virtex-7 FPGA VC709 Connectivity Kit is shipped with a 12 hour hardware time out evaluation netlist for the Northwest Logic PCIe DMA IP.
This 12 hour hardware time out evaluation netlist allows the customer to use this Netlist IP for evaluation purposes, however after 12 hours the PCIe DMA IP will time out in the hardware.
This time-out can be reset for another 12 hours by resetting the PCIe bus.
Once evaluation of the PCIe DMA provided is complete, Northwest Logic can be contacted to obtain a Full Production license.
This Northwest Logic Hardware Time Out Evaluation PCIe DMA Core is provided and configured with an AXI DMA Back End for use in the reference design that is provided with this kit.
If a different DMA interface or configuration is required (other than what is provided with the VC709), please contact Northwest Logic: http://nwlogic.com/info-request/
KC705 - Xilinx Kintex-7 FPGA KC705 Evaluation Kit
PCIe Lanes / Version: x4 Gen 2, x8 Gen 1
NWL Core: AXI DMA Back-End Core (2C2s, 2S2C)
The Xilinx Kintex-7 FPGA KC705 Evaluation Kit is shipped with a 12 hour hardware time out evaluation netlist for the Northwest Logic PCIe DMA IP.
This 12 hour hardware time out evaluation netlist allows the customer to use this Netlist IP for evaluation purposes, however after 12 hours the PCIe DMA IP will time out in the hardware.
This time-out can be reset for another 12 hours by resetting the PCIe bus.
Once evaluation of the PCIe DMA provided is complete, Northwest Logic can be contacted to obtain a Full Production license.
This Northwest Logic Hardware Time Out Evaluation PCIe DMA Core is provided and configured with an AXI DMA Back End for use in the reference design that is provided with this kit.
If a different DMA interface or configuration is required (other than what is provided with the KC705), please contact Northwest Logic: http://nwlogic.com/info-request/
Xilinx Kintex-7 FPGA Connectivity Kit
PCIe Lanes / Version: x8 Gen 2
NWL Core: AXI DMA Back-End Core (2C2s, 2S2C)
The Xilinx Kintex-7 FPGA Connectivity Kit is shipped with a 12 hour hardware time out evaluation netlist for the Northwest Logic PCIe DMA IP.
This 12 hour hardware time out evaluation netlist allows the customer to use this Netlist IP for evaluation purposes, however after 12 hours the PCIe DMA IP will time out in the hardware.
This time-out can be reset for another 12 hours by resetting the PCIe bus.
Once evaluation of the PCIe DMA provided is complete, Northwest Logic can be contacted to obtain a Full Production license.
This Northwest Logic Hardware Time Out Evaluation PCIe DMA Core is provided and configured with an AXI DMA Back End for use in the reference design that is provided with this kit.
If a different DMA Interface or configuration is required (other than what is provided with the Kintex-7 FPGA Connectivity Kit), please contact Northwest Logic: http://nwlogic.com/info-request/
AC701 - Xilinx Artix-7 FPGA AC701 Evaluation Kit
PCIe Lanes / Version: x4 Gen 2
NWL Core: AXI DMA Back-End Core (2C2s, 2S2C)
The Xilinx Artix-7 FPGA AC701 Evaluation Kit is shipped with a Full Production license for the Northwest Logic PCIe DMA IP.
This full production license allows the customer to use this NWL IP for evaluation, development, and deployment in production for all their Artix-7 based designs.
By default, the bitstream which gets generated in the AC701 TRD uses the evaluation version of the Northwest Logic DMA. If you need to generate the bitstream with full license (no hardware time-out), then these steps should be followed:
a. Navigate to a7_base_trd/hardware/sources/ip_package/nwl_x4g2/src
b. Rename dma_back_end_axi.vp to dma_back_end_axi_eval.vp
c. Copy the file a7_base_trd/hardware/sources/ip_package/nwl_x4g2_full/dma_back_end_axi.vp to a7_base_trd/hardware/sources/ip_package/nwl_x4g2/src/dma_back_end_axi.vp
d. Navigate to hardware/vivado/scripts and do vivado -source a7_base_trd_ipi.tcl
e. Click on Generate Bitstream in the Project Manager window. Click on OK to generate bitstream.
A window with message "Generate Bitstream Completed Successfully" will appear at the end of this process and a design bit file will be available in hardware/vivado/runs_ipi/a7_base_trd.runs/impl_1.
This Northwest Logic PCIe DMA Core is provided and configured with an AXI DMA Back End for use in the reference design that is provided with this kit.
If a different DMA interface or configuration is required (other than what is provided with the AC701), please contact Northwest Logic: http://nwlogic.com/info-request/
Xilinx Spartan-6 FPGA Connectivity Kit
PCIe Lanes / Version: x1 Gen 1
NWL Core: AXI DMA Back-End Core (2C2s, 2S2C)
This Xilinx Spartan-6 FPGA Connectivity Kit is shipped with a Full Production license for the Northwest Logic PCIe DMA IP.
This full production license allows the customer to use this NWL IP for evaluation, development, and deployment in production for all their Spartan-6 based designs.
This Northwest Logic PCIe DMA Core is provided and configured with an AXI DMA Back End for use in the reference design that is provided with this kit.
If a different DMA interface or configuration is required (other than what is provided with the Spartan-6 FPGA Connectivity Kit), please contact Northwest Logic: http://nwlogic.com/info-request/
Xilinx Virtex-6 FPGA Connectivity Kit
PCIe Lanes / Version: x8 Gen 2, x4 Gen 1
NWL Core: AXI DMA Back-End Core (2C2s, 2S2C)
This Xilinx Virtex-6 FPGA Connectivity Kit is shipped with a 12 hour hardware time out evaluation netlist for the Northwest Logic PCIe DMA IP.
This 12 hour hardware time out evaluation netlist allows the customer to use this Netlist IP for evaluation purposes, however after 12 hours the PCIe DMA IP will time out in the hardware.
This time-out can be reset for another 12 hours by resetting the PCIe bus.
Once evaluation of the PCIe DMA provided is complete, Northwest Logic can be contacted to obtain a Full Production license.
This Northwest Logic Hardware Time out Evaluation PCIe DMA Core is provided and configured with an AXI DMA Back End for use in the reference design that is provided with this kit.
If a different DMA interface or configuration is required (other than what is provided with the Virtex-6 FPGA Connectivity Kit), please contact Northwest Logic: http://nwlogic.com/info-request/
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 63512 | Xilinx Kit Portfolio - Information on Xilinx Design Suite Licenses included in Xilinx kits | N/A | N/A |