In 7 Series devices with multi-function HR I/O in banks 14 and bank 15, if the following conditions are met then the input might have an internal 0-1-0 transition to the interconnect logic during configuration startup:
Because this transition occurs after GWE enables the internal logic, it might affect the internal state of the device after configuration.
In a 7 series FPGA, this transition can occur at EOS (End Of Startup).
The HR I/O bank 34 and bank 35 in the Zynq-7000 SoC PL can have similar behavior.
No action is required for logic that is not impacted by input transitions during startup, (for example, logic that does not register inputs during startup or that is reset through/after startup).
The affected 7 Series FPGAs and Zynq-7000 SoCs and HR I/O banks are shown in Table 1:
Table 1 - 7 Series FPGAs and Zynq-7000 SoCs and HR I/O Banks Affected by Transition during Configuration Startup
A 7 series FPGA or Zynq-7000 SoC design can be affected when ALL of the following are TRUE:
When ALL of the above are TRUE, the internal signal from an input pin in an affected bank, might have a 0-1-0 transition at end of startup (EOS).
This internal input signal transition can affect the state of internal logic.
The internal input signal is clear of the potential transition by 200 nS after EOS.
Figure 1 HR I/O Bank 14/15/34/35 Potential Input Transition Window at EOS
Multiple options for work-arounds are available, including the following:
For the FPGA design work-arounds, an IGNORE_INP_B signal can be created using an EOS signal from the STARTUPE2 primitive and a suitably long counter or shift register to either delay the clock(s) to the affected logic or gate the affected input signals.
The active-High EOS output signal from the STARTUPE2 primitive signifies the end of configuration startup which begins the affected window of time.
Example block diagrams of potential FPGA design work-arounds are shown in Figure 2 and Figure 3, below.
Note: Figure 3 is a simplified, conceptual example.
Input gating can be implemented differently to assure release synchronous to logic clock(s).