AR# 66871

Description

In 7 Series FPGAs with multi-function HR I/O in banks 14/15 or in Zynq-7000 SoCs with HR I/O in banks 34/35, the HR I/O in those banks might have a 0-1-0 transition during power-on for the affected implementation shown below.

Affected Implementation - All of the following must be true for the potential I/O transition to occur:

• Bank 0 is operating at 1.8V or 1.5V.

• 7 Series FPGA banks 14/15 or Zynq-7000 SoC banks 34/35 are operating at 3.3V or 2.5V. (Thus these banks must be HR I/O banks.)

• The 3.3V or 2.5V VCCO power-on ramp for the 7 series FPGA banks 14/15 or Zynq-7000 SoC banks 34/35 is significantly delayed to near the completion of the power-on-reset time (Tpor) or later.
  Tpor begins after the last of the VCCINT/VCCBRAM/VCCAUX/VCCO_0 supplies to ramp (see UG470), ends with INIT_B released to HIGHZ, and the timing is defined in the device data sheet, typically 10 to 50 milliseconds.

• The I/O is not pulled High during power-on via an external or internal (i.e. PUDC_B=High) pull-up.

Impact:

When the affected implementation is present, the I/O in the 7 series FPGA banks 14/15 or Zynq-7000 SoC banks 34/35 can have 0-1-0 when the applicable bank VCCO ramps through the ~2.1V voltage level.

The duration of the 1 depends on the VCCO ramp rate and has been observed to range from a few microseconds up to 2 milliseconds, depending on the VCCO ramp rate. Slower VCCO ramp rates can result in longer duration of the 1.

Solution

To avoid the 0-1-0 transition in affected HR I/O banks, use one of the following solutions:

• Operate the affected HR I/O banks at the same voltage as bank 0.

• If the banks are operated at different voltages than those described in the affected implementation above, ensure that the affected HR I/O banks VCCO supply ramps above 2.3V at least 2 milliseconds prior to the end of power-on-reset (i.e. prior to INIT_B being released to HIGHZ).

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