AR# 66988

Description

This answer record contains the Release Notes and Known Issues for the UltraScale Architecture PHY for PCI Express Core and includes the following:

• General Information
• Known and Resolved Issues
• Revision History

This article is part of the PCI Express Solution Centre

Solution

Supported devices can be found in the following three locations:

• Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
• For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Tactical Patch

The following table provides a list of tactical patches for the UltraScale+ PCI Express Integrated Block core applicable on corresponding Vivado tool versions.

Known and Resolved Issues

The following table provides known issues for the UltraScale Architecture PHY for PCI Express core, starting with v1.0, initially released in Vivado 2016.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Other Information:

• NA
  

Xilinx Forums:

Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

Revision History: