This answer record contains the Release Notes and Known Issues for the UltraScale Architecture PHY for PCI Express Core and includes the following:
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
Supported devices can be found in the following three locations:
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version|
The following table provides a list of tactical patches for the UltraScale+ PCI Express Integrated Block core applicable on corresponding Vivado tool versions.
|Answer Record||Core Version (After installing the Patch)||Tool Version|
|(Xilinx Answer 71191)||v1.0 (Rev. 71191)||2018.1|
Known and Resolved Issues
The following table provides known issues for the UltraScale Architecture PHY for PCI Express core, starting with v1.0, initially released in Vivado 2016.1.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 71191)||Link does not train in Gen1 design with Refclk at 125 MHz and 250 MHz speeds||v1.0 (Rev8)||v1.0 (Rev8)|
Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
|08/06/2016||Updated for 2016.2 Release|
|10/05/2016||Updated for 2016.3 Release|
|01/24/2017||Updated for 2016.4 Release|
|04/05/2017||Updated for 2017.1 Release|
|06/12/2018||Added (Xilinx Answer 71191)|