AR# 68065

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SDK - XSDB halts processor at reset vector when a reset is triggered while debugging or running on Zynq-7000 or Zynq MPSoC

Description

While debugging or running an application on a Zynq-7000 or Zynq MPSoC device with the debugger attached to the target, triggering a reset causes the core to be halted at the reset vector:

xsct% connect
tcfchan#0
xsct% ta
  1  PS TAP
     2  PMU
     3  PL
  4  PSU
     5  RPU (Reset)
        6  Cortex-R5 #0 (RPU Reset)
        7  Cortex-R5 #1 (RPU Reset)
     8  APU
        9  Cortex-A53 #0 (Running)
       10  Cortex-A53 #1 (Power On Reset)
       11  Cortex-A53 #2 (Power On Reset)
       12  Cortex-A53 #3 (Power On Reset)
xsct% Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch)
xsct%

Solution

This is expected behavior.

By default, the System Debugger enables the vector catch feature to halt the processor core at the reset vector when a core reset is triggered.

This feature can be disabled for specific cores through XSDB using the configparams command:


xsct% connect -url 172.21.166.118:3121                                                                                                                                                                                                       
tcfchan#0
xsct% ta                                                                                                                                                                                                                                     
  1  PS TAP
     2  PMU
     3  PL
  4  PSU
     5  RPU (Reset)
        6  Cortex-R5 #0 (RPU Reset)
        7  Cortex-R5 #1 (RPU Reset)
     8  APU
        9  Cortex-A53 #0 (Running)
       10  Cortex-A53 #1 (Power On Reset)
       11  Cortex-A53 #2 (Power On Reset)
       12  Cortex-A53 #3 (Power On Reset)
xsct% configparams disable-access 1                                                                                                                                                                                                          
xsct% ta                                                                                                                                                                                                                                     
  1  PS TAP
     2  PMU
     3  PL
  4  PSU
     5  RPU (Access Disabled)
        6  Cortex-R5 #0 (RPU Access Disabled)
        7  Cortex-R5 #1 (RPU Access Disabled)
     8  APU (Access Disabled)
        9  Cortex-A53 #0 (APU Access Disabled)
       10  Cortex-A53 #1 (APU Access Disabled)
       11  Cortex-A53 #2 (APU Access Disabled)
       12  Cortex-A53 #3 (APU Access Disabled)

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
66297 SDK - Design Assistant N/A N/A
AR# 68065
Date 11/21/2018
Status Active
Type Solution Center
Tools
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