AR# 6831

V2.1i COREGEN USER GUIDE, VERILOG: "Error! Module name previously declared" / Verilog parent design example is incorrect

Description

Keywords: coregen, user guide, verilog, module

Urgency: hot

General Description:
In the Verilog design flow section of the 2.1i CORE Generator User guide,
the parent design myadder8_top.v ( on page 4-21) contains a redundant
module declaration for myadder8 which causes the followig error during
Verilog simulation:-

Error! Module name previously declared [Verilog-MNPO]

Solution

Remove the redundant module declaration from the parent design
before processing.

Currently the example reads:

//---------------------------------------------------
// synopsys translate_off
// edit the next line to reflect the actual path to
XilinxCoreLib
`include "/tools/xilinx/data/verilog/src/XilinxCoreLib/
adreVHT.v"
// synopsys translate_on
module top (A_P, B_P, C_P, CE_P, CI_P, CLR_P, S_P);
input [7 : 0] A_P;
input [7 : 0] B_P;
input C_P;
input CE_P;
input CI_P;
input CLR_P;
output [8 : 0] S_P;
// INST_TAG
myadder8 #(8, 1) myadder8_1 (
.A(A_P),
.B(B_P),
.C(C_P),
.CE(CE_P),
.CI(CI_P),
.CLR(CLR_P),
.S(S_P));
// INST_TAG_END
endmodule

module myadder8 (
A,
B,
C,
CE,
CI,
CLR,
S);
input [7 : 0] A;
input [7 : 0] B;
input C;
input CE;
input CI;
input CLR;
output [8 : 0] S;
// synopsys translate_off
ADREVHT #(8, 1) inst (.A(A_P),
.B(B_P),
.C(C_P),
.CE(CE_P),
.CI(CI_P),
.CLR(CLR_P),
.S(S_P));
// synopsys translate_on
endmodule


The redundant section is the module port declaration:

module myadder8 (
A,
B,
C,
CE,
CI,
CLR,
S);
input [7 : 0] A;
input [7 : 0] B;
input C;
input CE;
input CI;
input CLR;
output [8 : 0] S;
// synopsys translate_off
ADREVHT #(8, 1) inst (.A(A_P),
.B(B_P),
.C(C_P),
.CE(CE_P),
.CI(CI_P),
.CLR(CLR_P),
.S(S_P));
// synopsys translate_on
endmodule



AR# 6831
Date 08/01/2001
Status Archive
Type General Article