This answer record contains the Release Notes and Known Issues for the QDRII+ UltraScale and UltraScale+ cores and includes the following:
This Release Notes and Known Issues Answer Record is for the programmable logic QDRII+ IP core supported in UltraScale and UltraScale+ based devices.
QDRII+ IP Page:
Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
Supported devices can be found in the following locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.
Table 1 correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
|QDRII+ Version||Vivado Tools Version|
|v1.4 (Rev. 9)||2020.1|
|v1.4 (Rev. 8)||2019.2|
|v1.4 (Rev. 7)||2019.1|
|v1.4 (Rev. 6)||2018.3|
|v1.4 (Rev. 5)||2018.2|
|v1.4 (Rev. 4)||2018.1|
|v1.4 (Rev. 3)||2017.4|
|v1.4 (Rev. 2)||2017.3|
|v1.4 (Rev. 1)||2017.2|
|v1.3 (Rev. 1)||2016.4|
|v1.2 (Rev. 1)||2016.2|
For a list of supported memory interfaces and operating frequencies for UltraScale family FPGAs go to the External Memory Interfaces section of the Memory Solutions page:
For a complete list of supported QDRII+ memory devices refer to the memory_device_support_qdrIIplus.xlsx attachment found at the bottom of this Answer Record.
For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).
Known and Resolved Issues
Table 2 provides the known and resolved issues for the UltraScale family QDRII+ IP.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Table 2: Known and Resolved Issues
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 73714)||UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardware||v1.4 (Rev. 9)||NF|
|(Xilinx Answer 71400)||UltraScale/UltraScale+ QDRII+ IP - Byte 3 of a 36-bit QDRII+ Interface Not Showing Calibration Margins in the Hardware Manage||v1.2||Will not be fixed|
|(Xilinx Answer 68751)||UltraScale/UltraScale+ QDRII+ IP - Are GSI memory models supported in simulation?||v1.3 (Rev. 1)||Not a bug|
|(Xilinx Answer 67959)||UltraScale/UltraScale+ QDRII+ IP - XSDB reports Memory Frequency incorrectly||v1.2 (Rev. 1)||v1.4 (Rev. 6)|
|(Xilinx Answer 67336)||UltraScale/UltraScale+ QDRII+ IP - *_ooc.xdc constraints file does not get generated in Out-Of-Context (OOC) mode||v1.2 (Rev. 1)||Will not be fixed|
|(Xilinx Answer 64783)||UltraScale/UltraScale+ QDRII+ IP - XSDB Debugger indicates MicroBlaze has failed but calibration completes||v7.0||v1.0|
|(Xilinx Answer 64488)||UltraScale/UltraScale+ QDRII+ IP - Core generation fails due to invalid Memory Device Interface Speed setting||v7.0||v7.1|
|(Xilinx Answer 64006)||UltraScale/UltraScale+ QDRII+ IP - Unexpected DRC for correct placement of memory clock pair (K/K#)||v7.0||v7.1|
|(Xilinx Answer 63689)||UltraScale/UltraScale+ QDRII+ IP - Read latency 2.0 (RL2) and Burst length 2 (BL2) designs fail simulation with Cypress memory model||v7.0||v7.1|
|(Xilinx Answer 64427)||UltraScale/UltraScale+ QDRII+ IP - Calibration and intermittent data errors due to improper calibration results||v6.1||v7.0|
|(Xilinx Answer 63261)||UltraScale/UltraScale+ DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT check||v6.1||v7.0|
|(Xilinx Answer 62157)||Design Advisory for UltraScale/UltraScale+ QDRII+ IP - Pinout DRC violations not caught in I/O Planner||v5.0 Rev1||v6.0|
|(Xilinx Answer 61555)||UltraScale/UltraScale+ QDRII+ IP - Multi-driver issue in Cypress memory model causes data errors in simulation||v5.0 Rev1||N/A|
|(Xilinx Answer 60951)||UltraScale/UltraScale+ RLDRAM3 and QDRII+ - Timing failure from XiPHY to riu_clk||v5.0 Rev 1||v6.0|
|(Xilinx Answer 60047)||UltraScale/UltraScale+ QDRII+ IP - Incorrect parameter values for 36-bit designs using x18 components||v5.0||N/A|
|04/18/2017||Created Separate Answer Record for QDRII+|
|06/12/2017||Updated for 2017.2; Added (Xilinx Answer 68028), (Xilinx Answer 69291)|
|06/22/2017||Added (Xilinx Answer 69324)|
|07/31/2017||Updated debugging link to (Xilinx Answer 68937)|
|12/12/2017||Updated for 2017.4|
|03/13/2018||Updated for 2018.1|
|08/02/2018||Added (Xilinx Answer 71400), Updated for 2018.2|
|09/20/2018||Updated for 2018.3|
|05/02/2019||Updated for 2019.1|
|10/21/2019||Updated for 2019.2|
|05/21/2020||Added AR#73714; Updated for 2020.1|
|Name||File Size||File Type|