The Design Advisory covers the Zynq-7000 SoC RSVDGND pin.
This pin is reserved for Xilinx testing only, and Xilinx recommends that the pin be left unconnected.
By default, the RSVDGND pin is an input. However, when the STARTUPE2 primitive is instantiated in a PL design, the STARTUPE2.USRCCLKTS port setting can override the pin controls and cause the RSVDGND pin to drive out the given STARTUPE2.USRCCLKO value.
As a result, when a Zynq-7000 SoC PL design uses the STARTUPE2 primitive, the STARTUPE2.USRCCLKTS port must be tied to 1 and the STARTUPE2.USRCCLKO port must be tied to 0.
Vivado 2017.3 and later tools include a DRC that checks for use of the STARTUPE2 primitive, and if it is used, also checks that the USRCCLKTS and USRCCLKO ports are tied to the required safe values.
Zynq-7000 SoC PL designs built with all versions of ISE or Vivado design tools version 2017.2 or earlier, should be checked for use of the STARTUPE2 primitive.
If it is used, also check that STARTUPE2.USRCCLKTS=1 or STARTUPE2.USRCCLKO=0, as shown in the figure below:
The Vivado utilization report (*utilitization*.rpt) file that is generated by the report_utilization command indicates the use (or not) of the STARTUPE2 primitive.
An example of the section of the report that displays the STARTUPE2 utilization follows:
A utilization of 0.00% means the STARTUPE2 is not used. A utilization of 100.00% means the STARTUPE2 is used.
If a Zynq-7000 SoC PL design is affected by improper port settings of an instantiated STARTUPE2 primitive, then the design should be updated with the required safe STARTUPE2 port settings, specified above.
Impact to Affected Designs:
If a Zynq-7000 SoC PL design is affected by improper port settings of an instantiated STARTUPE2 primitive, the RSVDGND pin can be damaged.
If damage occurs, then the majority of cases result in no impact to the device operation because the RSVDGND pin is not used during normal operation.