AR# 70706

DMA/Bridge Subsystem for PCI Express (Bridge Mode/Root Port - Vivado 2017.4) - Bridge Mode - Root Port - AXI transactions fail when no Endpoint is connected

Description

Version Found: v4.0 (Rev1)

Version Resolved and other Known Issues: (Xilinx Answer 65443), (Xilinx Answer 70702)

When using the DMA/Bridge Subsystem for PCI Express in Bridge Mode (UltraScale+), the bridge registers are held in reset until user_reset is released by default. 

For Root Port mode, this means that bridge registers (accessed via S_AXI_CTL bus) are unavailable for access and will not respond if no Endpoint device is connected.

Used in combination with Zynq UltraScale+ MPSoC as a PL PCIe Root Port, and with the pcie-xdma-pl driver, this will cause PetaLinux to hang on boot.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

For Vivado 2017.4 and prior versions, the Bridge register reset can be changed to the Phy_ready signal via the IP Configuration, as shown below.

When using this selection, all AXI Slave Interface data path accesses should be held until the user_lnk_up output signal is high, or Link Up is confirmed via the Bridge PHY Status/Control Register Link Up bit (as described in (PG194) - AXI Bridge for PCI Express Gen3).

 


 

The default selection of the AXI Bridge - Root Port mode reset source has been changed to phy_ready beginning in the 2018.1 version of the core.

Revision History:

06/05/2018 - Initial Release

Linked Answer Records

Master Answer Records

AR# 70706
Date 06/05/2018
Status Active
Type Known Issues
IP