This Design Advisory covers the use of AXI SmartConnect with a DMA/Bridge Subsystem for PCI Express or QDMA Subsystem.
AXI SmartConnect does not utilize the AxCache - non-modification bit of the AXI-4 Protocol.
AXI SmartConnect might upsize a request from the AXI Master even when the AxCache - non-modification bit is set.
For the PCI Express IPs this can lead to a memory access larger than intended, violating the protocol for a non-prefetch BAR.
In the case of a PCI Express IP configured as a Root Port, some connected Endpoint devices might experience fatal errors, crash, or have data corruption due to the unintended access of memory space.
If the user design has any non-prefetch or non-modifiable memory elements connected via a PCIe Express Bridge IP (DMA/Bridge Subsystem for PCI Express, QDMA Subsystem), an AXI SmartConnect should not be used anywhere in the affected data path.
AXI Interconnect should be used instead.
A tactical patch fix for Vivado 2018.3 is available in (Xilinx Answer 71869).
The issue is scheduled to be fixed in the next release.