AR# 70838

Design Advisory for AXI Smartconnect with PCI Express IP - Interoperability Issue - Data request upsize causes potential data corruption


This Design Advisory covers the use of AXI SmartConnect with a DMA/Bridge Subsystem for PCI Express or QDMA Subsystem.

AXI SmartConnect does not utilize the AxCache[1] - non-modification bit of the AXI-4 Protocol.

AXI SmartConnect might upsize a request from the AXI Master even when the AxCache[1] - non-modification bit is set.

For the PCI Express IPs this can lead to a memory access larger than intended, violating the protocol for a non-prefetch BAR.

In the case of a PCI Express IP configured as a Root Port, some connected Endpoint devices might experience fatal errors, crash, or have data corruption due to the unintended access of memory space.


If the user design has any non-prefetch or non-modifiable memory elements connected via a PCIe Express Bridge IP (DMA/Bridge Subsystem for PCI Express, QDMA Subsystem), an AXI SmartConnect should not be used anywhere in the affected data path.

AXI Interconnect should be used instead.

A tactical patch fix for Vivado 2018.3 is available in (Xilinx Answer 71869).

The issue is scheduled to be fixed in the next release.

Revision History:

  • 04/25/2018 - Initial Release
  • 03/28/2019 - Added information on Vivado 2018.3 patch availability.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
70702 Zynq UltraScale+ MPSoC - PS/PL PCIe Drivers - Release Notes N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
71869 SmartConnect - Narrow single accesses are improperly resized N/A N/A
AR# 70838
Date 03/28/2019
Status Active
Type Design Advisory
IP More Less