AR# 71169

Xilinx PCI Express (Vivado 2018.1) - Core left shifts the values of MSIX_CAP_TABLE_OFFSET and MSIX_CAP_PBA_OFFSET parameters by 3 bits

Description

The MSIX table offset' parameter of the core is erroneously shifted by 3 bits.

The core left shifts the values of MSIX_CAP_TABLE_OFFSET and MSIX_CAP_PBA_OFFSET parameters by 3 bits.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

This is a known issue to be fixed in Vivado 2018.2.

This issue applies to all IPs below:

  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe);
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe);
  • 7 Series Integrated Block for PCI Express (PCIe);
  • AXI PCIe Gen3;
  • AXI PCI Express (PCIe) Gen2;
  • DMA Subsystem for PCI Express
  • Queue DMA subsystem for PCI Express

To fix the issue in Vivado 2018.1 (except for AXI PCI Express Gen2, the fix for which will be included in Vivado 2018.2), please install the patch attached with this answer record. 

For instructions on installing the patch, please check the instructions in the 'patch_readme' directory in the attached patch file.

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History

06/05/2018 - Initial release

Attachments

Associated Attachments

Name File Size File Type
AR71169_Vivado_2018_1_preliminary_rev1.zip 11 MB ZIP
AR# 71169
Date 06/18/2018
Status Active
Type Known Issues
IP More Less