AR# 71424

Description

This is the Master Answer Record for the ZCU111 RF Data Converter Evaluation Tool.

It lists known issues and limitations for Version 1.4 of the ZCU11 Evaluation Tool.

Solution

Limitations:

1. FFT Size

In BRAM mode, the current design does not support sample sizes above 64K for Real or 32K for IQ.

The sample size should be a multiple of 32 bytes.

2. Vivado Windows path length issue

When running Vivado on a Windows platform, the user can encounter a project path length issue.

The error is most common when generating IP source files or when archiving a project. Please see (Xilinx Answer 52787) for information on handling this issue.

3. External RF PLL Supported Frequency

Currently a set of 26 frequencies can be generated using the Evaluation Tool for External RF PLLs (LMX) and only a single frequency for LMK PLL (122.88 MHz).

4. Interpolation/Decimation

The Fabric output clock is common for Tile Fabric logic so the Interpolation/Decimation rate must be the same across the tile.

5. MTS

For MTS, only one clock frequency of value 3932.16MHz is supported for ADC and DAC.

6. Frequency

The GUI displays an error when the External PLL frequency is set to 102.406 MHz. Once the error appears, the user must restart the board and choose a frequency above this value.

7. Error checks

There are three separate designs in this release. User needs to make sure that the tests are done according to the feature table in the Wiki.

The GUI will return an error if user tries to violate the guidance in the table.

8. PAT tool

The Power Analysis Tool (PAT) must be checked only for Non-MTS_8x8 design. Other designs have PAT enabled but do not show correct values.

Known Issues:

Listed below are the known issues and limitations in this release:

Mixer and Sampler Frequency:

When the user is setting both mixer frequency and sampling frequency, the mixer frequency can get altered.
Users might need to re-correct the mixer frequency after setting the Sampling frequency.

Clock settings button:

The “Clock settings” button might not work in some cases.
To work around this issue, click on another button or another view, then click the “Clock settings” button again.

Long run time:

When compiling the design on Vivado using a Windows machine, users might a long run time to the order of 12+ hours.
This has been observed on a quad-core machine. The run time on Linux machine with 16+ cores is observed to be 3-4 hours.

UI Error 85:

This will occur when the data is still being captured or generated and a control command is sent to the design.

It can also occur when in “loop mode” on the ADC side.

Error 5099:

In MTS mode, on pressing Synchronization, Error 5099 will display in the UI as shown in the figure below, once in every 10 times.

The user needs to restart the board and re-run the test to validate MTS.

RFDC configuration to meet timing:

After creating a design for 1x1 SSR IP, the user needs to make sure the DAC and ADC settings of the disabled RFDC channels are as shown in the snapshot below.

The design will not meet timing if the settings are different.

Rftool fails to come up for clocking modification of U104 Channel B.

This issue will result in the error "could not set ADC/DAC tile 1 to "frequency" ret = 1."

To work around the issue, in the rfdc_interface.c file (present in the rftool application), comment out the return value of XRFdc_DynamicPLLConfig() in the rfdc_init() function.