AR# 71427

AXI Bridge for PCI Express Gen3 / UltraScale FPGA Gen3 Integrated Block for PCI Express / DMA Subsystem for PCI Express (Vivado 2018.2) - ERROR: [DRC REQP-1910] PCIE31_invalid_MCAPPERSTxB_driver

Description

The following DRC is triggered during opt_design if you have a dedicated reset routing enabled in the AXI Bridge for PCI Express Gen3 core and you drive logic into sys_rst. 

This example has a LUT1 driving the sys_rst port with the dedicated reset routing enabled.

ERROR: [DRC REQP-1910] PCIE31_invalid_MCAPPERSTxB_driver: axi_pcie3_0/inst/pcie3_ip_i/inst/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst pin MCAPPERST0B has an invalid driver LUT1.
Only a direct connection from a Port or IBUF/IBUF_ANALOG may drive this pin.

This issue applies to the AXI Bridge for PCI Express Gen3 / UltraScale FPGA Gen3 Integrated Block for PCI Express / DMA Subsystem for PCI Express.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

When the core is in "Basic Mode" and you are using a PCIe Block Location that supports Tandem, dedicated reset routing is turned on by default.

The recommended guideline is as follows:

In the core configuration GUI, uncheck "Use dedicated PERST routing Resources"

Revision History:

09/03/2018 - Initial release

AR# 71427
Date 09/03/2018
Status Active
Type General Article
Devices
Tools
IP