AR# 71634

DMA/Bridge Subsystem for PCI Express (Vivado 2018.2) - Issue in AXI2PCIe translation when the PCIe address is greater than 32 bits and AXI address is fewer than 64 bits

Description

Version Found: v4.(Rev1)

Version Resolved and other Known Issues: (Xilinx Answer 65443)

"AXI to PCIe Translation" does not work correctly when the PCIe address is greater than 32 bits and the AXI address is fewer than 64 bits.

If the AXI Address Width is set to 64 bits, the address translation works correctly.

The issue applies to both Endpoint and RootPort configurations.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

This is a known issue to be fixed in a future release of the core.

To fix the issue in Vivado 2018.2, please install the patch provided in this answer record.

For instructions on installing the patch, please check the instructions in the 'patch_readme' directory in the attached patch file.

Revision History:

11/05/2018 - Initial Release

Attachments

Associated Attachments

AR# 71634
Date 11/29/2018
Status Active
Type Known Issues
IP