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AR# 71718

DMA / Bridge Subsystem for PCI Express and UltraScale+ PCI Express Integrated Block (Vivado 2018.2) - x4 Gen3 Root Port IP generation fails in XAZU5EV-SFVC784-1Q-q device

Description

Version Found:

  • DMA / Bridge Subsystem for PCI Express v4.1 (Rev. 1) - (Vivado 2018.2)
  • UltraScale+ PCI Express Integrated Block v1.3 (Rev. 3) - (Vivado 2018.2)

Version Resolved and other Known Issues: DMA Subsystem for PCI Express (Xilinx Answer 65443) / UltraScale+ PCI Express Integrated Block (Xilinx Answer 65751)

The issues listed in the patch might have existed in previous versions of the core.

The tactical patch provided with this Answer Record provides the following fixes and enhancements:

DMA / Bridge Subsystem for PCI Express v4.1 (Rev. 1) - (Vivado 2017.2) and UltraScale+ PCI Express Integrated Block v1.3 (Rev. 3) - (Vivado 2018.2)

  • Bug Fix: Allow x4 gen3 RP generation with XAZU5EV-SFVC784-1Q-q

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

The issues listed in this answer record will be fixed in a future release of the core.

For instructions on installing the patch, please check the instructions in the 'patch_readme' directory in the attached patch file.

Note: The "Version Found" lists the version where the problem was first discovered.

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Attachments

Associated Attachments

Name File Size File Type
AR71718_Vivado_2018_2_preliminary_rev2.zip 6 MB ZIP
AR# 71718
Date 02/28/2019
Status Active
Type Known Issues
Devices
Tools
IP
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