In a design with "Internal Tag Management" enabled and the straddling option disabled, pcie_rq_tag_vld1 is asserted when consecutive reads are initiated on the s_axis_rq_* interface.
However, the IP product guide (PG213) seems to indicate it should not be asserted with the following statement:
"When the Straddle option is disabled, only pcie_rq_tag_vld0 is used."
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
The statement provided in (PG213) is not correct. (PG213) will be updated with the following statement in the next release of the document.
"Use of pcie_rq_tag_vld0 & pcie_rq_tag_vld1 are orthogonal to whether the 'Straddle' option is enabled. The PCIe core could use either of the vld0/vld1 ports to showcase the valid tags".
11/21/2018 - Initial Release